NXP Semiconductors CBT3125PW/G-T
- Part No.:
- CBT3125PW/G-T
- Manufacturer:
- NXP Semiconductors
- Category:
- Signal Switches, Multiplexers, Decoders
- Package:
- 14-TSSOP (0.173", 4.40mm Width)
- Datasheet:
-
CBT3125PW/G-T.pdf
- Description:
- IC BUS SWITCH 1 X 1:1 14TSSOP
- Quantity:
- Payment:

- Shipping:

Inventory:1,878
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Product details
Overview
CBT3125PW/G-T from Nexperia is a quadruple FET bus switch with independent 14-pin TSSOP package, 5 Ω typical ON resistance at 4.5 V, TTL-compatible inputs, and active-low enable control per channel. It isolates or connects data paths in high-speed digital systems such as address/data buses in microcontroller peripherals and memory interfaces.
For engineers reviewing the CBT3125PW/G-T datasheet, CBT3125PW/G-T pinout, CBT3125PW/G-T application, or CBT3125PW/G-T equivalent, this page delivers verified pin functions, real-world switching performance (0.25 ns max propagation delay), thermal and ESD specs (HBM >2000 V), and direct alternatives for bus isolation design.
Technical Context
The CBT3125PW/G-T implements four independent bidirectional analog switches using enhancement-mode NMOS FETs, each controlled by a dedicated active-low output enable (nOE) input. Switching occurs without level translation, supporting rail-to-rail signal pass-through between A and B ports.
Each channel operates with <7 Ω ON resistance at 4.5 V supply and exhibits sub-5 ns enable/disable timing. The device requires no external biasing, draws only 3 μA quiescent current, and maintains <3.4 pF off-state capacitance to minimize signal integrity degradation in high-frequency bus environments.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| ON Resistance | 5 Ω typical at VCC = 4.5 V, II = 64 mA - ensures minimal voltage drop and signal attenuation on 5 V digital buses |
| Propagation Delay | 0.25 ns max (nA↔nB) - supports >10 MHz bus switching without timing violation |
| Enable/Disable Time | 1.0–5.4 ns (ten), 1.0–4.7 ns (tdis) - enables precise synchronous bus gating in clocked systems |
| Input Voltage Range | −0.5 V to +7.0 V - allows safe interfacing with mixed-voltage logic families including 3.3 V and 5 V domains |
| ESD Protection | HBM >2000 V, MM >200 V, CDM >1000 V - meets industrial-grade robustness requirements without external protection |
| Supply Current | 3 μA max at VCC = 5.5 V - negligible power impact in always-on or low-power standby modes |
| Off-State Capacitance | 3.4 pF max - minimizes crosstalk and loading on adjacent high-speed traces |
Pinout & Package
TSSOP14 package (SOT402-1): plastic thin shrink small outline, 14 leads, body width 4.4 mm, 0.65 mm lead pitch, exposed pad not present.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 4, 10, 13 | 1OE, 2OE, 3OE, 4OE | Active-low enable inputs - drive LOW to connect corresponding A-B channel; HIGH disables isolation |
| 2, 5, 9, 12 | 1A, 2A, 3A, 4A | Data inputs/outputs (bidirectional) - connected directly to source-side bus segments |
| 3, 6, 8, 11 | 1B, 2B, 3B, 4B | Data inputs/outputs (bidirectional) - connected directly to sink-side bus segments |
| 7 | GND | Ground reference - must be low-impedance connection to minimize noise coupling into switch paths |
| 14 | VCC | Positive supply - powers internal FET gates; decoupling capacitor required within 1 cm of pin |
Key Features
| Feature | Design Value |
|---|---|
| Standard '125'-type pinout | Pin-compatible with industry-standard 74LVC1G125 and SN74LVC1G125 footprints - simplifies legacy board reuse |
| 5 Ω ON resistance | Enables <50 mV voltage drop at 10 mA bus current - preserves logic HIGH margin across full temperature range |
| TTL-compatible inputs | VIH ≥ 2.0 V, VIL ≤ 0.8 V - interoperates directly with 5 V CMOS and TTL logic without level shifters |
| Latch-up immunity | Exceeds 500 mA per JESD78 - prevents destructive latch-up during hot-swap or bus contention events |
| Low dynamic power | ΔICC ≤ 2.5 mA per enabled input - avoids supply droop when multiple channels activate simultaneously |
Applications
| PCI Express Slot Isolation | Microcontroller Address Bus Multiplexing |
|---|---|
|
Use Scenario: Isolating PCIe configuration space access between host CPU and add-in card during hot-plug enumeration. IC Role / Device Role / Timing Role: Bidirectional bus switch enabling/disabling MUX-controlled address/data lines under firmware control. Use Value: Prevents back-driving and contention during card insertion/removal while maintaining <0.25 ns signal integrity for 2.5 GT/s link training. |
Use Scenario: Sharing a single 8-bit data bus between an MCU and two peripheral ICs (e.g., ADC and DAC) via time-division multiplexing. IC Role / Device Role / Timing Role: Four-channel directional gate synchronizing with MCU GPIO-controlled OE signals to route data without bus contention. Use Value: Eliminates need for tristate buffers or complex bus arbitration logic; 5 Ω RON ensures <1% signal distortion at 10 MHz operation. |
| Legacy ISA Bus Signal Conditioning | Industrial I/O Module Data Path Switching |
|
Use Scenario: Adding hot-swap capability to ISA-bus expansion slots by inserting bus switches between slot edge connector and system backplane. IC Role / Device Role / Timing Role: Quad-channel isolation device controlled by slot presence detection logic to enable/disable bus access pre-initialization. Use Value: Meets JESD78 latch-up immunity (>500 mA) and HBM ESD rating (>2000 V) required for field-replaceable module interfaces. |
Use Scenario: Routing sensor analog outputs or digital status signals through configurable I/O modules in programmable logic controllers (PLCs). IC Role / Device Role / Timing Role: Low-capacitance (3.4 pF off-state) bidirectional switch enabling flexible signal path reconfiguration via FPGA-controlled OE pins. Use Value: Maintains signal fidelity for 0–10 V analog monitoring and 24 V digital I/O while supporting firmware-based topology changes without hardware modification. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar FET bus switch applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74LVC1G125DBVR | Single-channel, SOT-23-5 package; 3.7 Ω RON at 3.3 V; 1.8–5.5 V supply range | Requires four units for quad functionality; better suited for distributed point-of-load switching than consolidated bus isolation | Select when board space permits discrete channel placement and 3.3 V operation dominates |
| 74LVC125APW | Quad non-inverting buffer with 3-state outputs; 24 mA drive; 3.3 V only; no analog pass-through | Provides logic-level buffering but lacks true bidirectional analog switching - unsuitable for passive bus isolation | Choose only if active driving (not passive gating) is required and voltage translation is unnecessary |
Compared with SN74LVC1G125DBVR and 74LVC125APW, the CBT3125PW/G-T uniquely delivers quad bidirectional analog switching in one TSSOP14 package with 5 V tolerance, sub-5 ns timing, and proven industrial ESD/latch-up robustness - making it optimal for consolidated, high-integrity bus isolation where signal transparency and reliability are critical.
Availability
CBT3125PW/G-T is available at Aetrix Electronics and suitable for PCI Express hot-plug interfaces, microcontroller peripheral multiplexing, legacy ISA bus upgrades, and industrial I/O module signal routing requiring stable component supply and long-term manufacturability.
Supply support for CBT3125PW/G-T includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert delivering high-performance logic, analog, and MOSFET solutions optimized for efficiency, reliability, and scalability in industrial, computing, and consumer applications.
The CBT3125PW/G-T belongs to Nexperia's legacy bus switch family designed specifically for low-distortion, high-speed digital signal isolation in 5 V systems - emphasizing robustness, pin compatibility, and minimal design overhead.
FAQ
What is the maximum operating voltage for CBT3125PW/G-T?
The CBT3125PW/G-T supports a supply voltage (VCC) range of −0.5 V to +7.0 V absolute maximum, with recommended operation between 4.5 V and 5.5 V. This 5 V nominal rating ensures compatibility with standard TTL and CMOS logic families while providing margin against transient overvoltage events on the bus side.
Does CBT3125PW/G-T support bidirectional signal flow?
Yes, the CBT3125PW/G-T provides true bidirectional analog switching between each A and B port pair. Signals pass with equal low impedance (<7 Ω) in either direction when the associated nOE pin is LOW, enabling use in shared data/address buses without direction control logic.
How does the enable logic work on CBT3125PW/G-T?
Each of the four channels has its own active-low output enable input (1OE–4OE). When an nOE pin is driven LOW, the corresponding A–B switch turns ON; when HIGH, the channel enters high-impedance OFF state. All four enables operate independently, allowing selective bus segmentation.
Is CBT3125PW/G-T suitable for 3.3 V logic systems?
Yes - although optimized for 5 V operation, the CBT3125PW/G-T accepts input voltages from −0.5 V to +7.0 V and functions reliably down to 4.5 V supply. Its TTL-compatible inputs (VIH ≥ 2.0 V, VIL ≤ 0.8 V) interface cleanly with 3.3 V logic outputs when VCC = 5 V, and its 5 Ω RON remains stable across the full operating range.
What thermal and reliability qualifications does CBT3125PW/G-T meet?
The CBT3125PW/G-T is rated for operation from −40 °C to +85 °C ambient, exceeds 500 mA latch-up immunity per JESD78, and achieves HBM ESD protection >2000 V, MM >200 V, and CDM >1000 V. These ratings confirm suitability for industrial environments with frequent handling and electrical transients.
CBT3125PW/G-T Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Series:
- 74CBT
- Package/Case:
- 14-TSSOP (0.173", 4.40mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Type:
- Bus Switch
- Circuit:
- 1 x 1:1
- Independent Circuits:
- 4
- Current - Output High, Low:
- -
- Voltage Supply Source:
- Single Supply
- Voltage - Supply:
- 4.5V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 14-TSSOP
CBT3125PW/G-T FAQ
1.How can I place an order for CBT3125PW/G-T through Aetrix?
Please submit a Request for Quotation (RFQ) for CBT3125PW/G-T on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for CBT3125PW/G-T reliable?
The price and inventory of CBT3125PW/G-T are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for CBT3125PW/G-T is usually 5 days.
3.What payment methods are accepted for CBT3125PW/G-T?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for CBT3125PW/G-T transactions.
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4.How is shipping managed for CBT3125PW/G-T?
CBT3125PW/G-T orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your CBT3125PW/G-T order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for CBT3125PW/G-T?
For technical support, including CBT3125PW/G-T datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your CBT3125PW/G-T requirements.
6.How does Aetrix verify that CBT3125PW/G-T is sourced from the original manufacturer or authorized distributors?
All CBT3125PW/G-T products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that CBT3125PW/G-T meets industry standards.
7.What is the process for return or replacement of CBT3125PW/G-T?
All CBT3125PW/G-T units undergo pre-shipment inspection (PSI). If there is an issue with CBT3125PW/G-T, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The CBT3125PW/G-T part is unused and in its original packaging.
Return procedure for CBT3125PW/G-T:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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