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Texas Instruments CD4007UBMT
- Part No.:
- CD4007UBMT
- Manufacturer:
- Texas Instruments
- Category:
- Specialty Logic
- Package:
- 14-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
CD4007UBMT.pdf
- Description:
- IC DUAL COMPL PAIR W/INV 14SOIC
- Quantity:
- Payment:
- Shipping:
Inventory:1,160
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Product details
Overview
CD4007UBMT from Texas Instruments is a dual complementary pair plus inverter CMOS array IC used for discrete transistor-level circuit prototyping, biasing networks, and analog switch design. It integrates three matched N-channel and three matched P-channel MOSFETs with shared gates and drains, operates from 3 V to 18 V supply, supports -55°C to +125°C temperature range, and features low input current (≤100 pA) and high noise immunity (≥50% VDD).
For engineers reviewing the CD4007UBMT datasheet, CD4007UBMT pinout, CD4007UBMT application, or CD4007UBMT equivalent, this device serves as a flexible building block for custom logic, current mirrors, differential pairs, and rail-to-rail analog switching - especially where discrete FET matching and dual-polarity operation are required without external component count increase.
Technical Context
The CD4007UBMT implements a fixed internal topology: two complementary MOSFET pairs (N1/P1 and N2/P2) sharing source terminals, plus an independent inverter stage (N3/P3) with common drain output. All transistors share identical process characteristics, enabling precise ratio-matching and thermal tracking.
It functions as a programmable analog/digital primitive - not a logic gate IC - requiring external connection of gates, sources, and drains to configure amplifiers, switches, or current sources. Its operation depends entirely on user-defined terminal interconnections, with no internal logic or clocking.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage Range | 3 V to 18 V - Enables direct interface with legacy 5 V, 12 V, and battery-powered systems without level-shifting. |
| Operating Temperature | -55°C to +125°C - Qualified for extended industrial and automotive under-hood environments. |
| Input Leakage Current | ≤100 pA at 18 V - Ensures minimal bias error in high-impedance analog nodes and precision current mirrors. |
| Logic Threshold | VDD/2 ±10% - Provides predictable switching point across voltage range for reliable inverter operation. |
| Output Drive Capability | ±4.2 mA at VDD = 15 V - Sufficient to drive capacitive loads up to ~50 pF or interface with TTL/CMOS inputs. |
| Propagation Delay | 120 ns typical at VDD = 10 V - Supports low-speed digital control and analog sampling timing up to ~1 MHz. |
Pinout & Package
CD4007UBMT is supplied in a 14-lead small-outline integrated circuit (SOIC) package (Package Drawing D), 3.9 mm wide, 1.75 mm max height, with 1.27 mm pitch and gull-wing leads. Pin 1 is located at the top-left corner with notch or index mark.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | N-Channel Gate 1 / P-Channel Gate 1 | Common gate node for first complementary pair - used for input signal or bias control. |
| 2 | N-Channel Drain 1 / P-Channel Source 1 | Shared drain-source junction - configured as common-drain (source follower) or common-source node. |
| 3 | P-Channel Drain 1 / N-Channel Source 1 | Complementary output node for first pair - polarity inversion point when used as inverter. |
| 4 | N-Channel Source 2 / P-Channel Drain 2 | Second pair's inverted output node - enables differential pair or cascode configuration. |
| 5 | P-Channel Source 2 / N-Channel Drain 2 | Second pair's shared junction - used for current mirror reference or active load. |
| 6 | N-Channel Gate 2 / P-Channel Gate 2 | Independent gate for second complementary pair - allows separate biasing or signal injection. |
| 7 | VSS | Ground reference for all N-channel sources - must be connected to system low potential. |
| 8 | VDD | Positive supply for all P-channel sources - defines logic high and analog rail limits. |
| 9 | N-Channel Drain 3 | Inverter stage N-FET drain - connects to output when P-FET source is tied to VDD. |
| 10 | P-Channel Drain 3 | Inverter stage P-FET drain - ties to same output node as Pin 9 for push-pull action. |
| 11 | N-Channel Source 3 / P-Channel Source 3 | Common source node for inverter - forms output pull-down/pull-up path with Pins 9 and 10. |
| 12 | N-Channel Gate 3 / P-Channel Gate 3 | Inverter input - high-impedance CMOS gate accepting logic or analog control signals. |
| 13 | P-Channel Drain 3 / N-Channel Drain 3 | Redundant output connection - electrically tied to Pins 9 and 10 for robust output routing. |
| 14 | N-Channel Source 3 / P-Channel Source 3 | Redundant source tie - ensures low-impedance connection to VSS/VDD for inverter stage. |
Key Features
| Feature | Design Value |
|---|---|
| Matched N- and P-channel FET pairs | Guaranteed threshold voltage tracking within ±100 mV enables accurate current mirroring and differential gain stability. |
| No internal connections between sections | Full user-defined interconnection freedom - each transistor terminal is externally accessible for custom topology synthesis. |
| High input impedance (≥1012 Ω) | Prevents loading of high-Z sensor outputs or feedback networks in op-amp and comparator circuits. |
| Rail-to-rail output swing | Drives within 0.5 V of VSS and VDD - preserves dynamic range in single-supply analog signal paths. |
| ESD protection diodes on all pins | Withstands ≥2 kV HBM - reduces need for external protection in lab and low-risk production environments. |
Applications
| Current Mirror Biasing | Differential Amplifier Core |
|---|---|
Use Scenario: Generating stable, temperature-compensated bias currents for op-amp input stages or power amplifier quiescent points. IC Role / Device Role / Timing Role: CD4007UBMT provides matched N- and P-channel FETs configured as Wilson or cascode current mirrors with <1% ratio error over temperature. Use Value: Eliminates need for discrete matched FETs or precision resistors, reducing BOM count and layout area while improving thermal tracking. |
Use Scenario: Constructing discrete-input, high-common-mode-rejection amplifiers for sensor front-ends or instrumentation signal conditioning. IC Role / Device Role / Timing Role: CD4007UBMT supplies thermally coupled N- and P-channel pairs as active load and input transistors in folded-cascode topology. Use Value: Achieves >70 dB CMRR at DC without laser-trimmed resistors, leveraging inherent process matching of on-die FETs. |
| Analog Switch Matrix | Programmable Logic Element |
Use Scenario: Routing multiple analog signals (e.g., multiplexed thermocouple or strain gauge inputs) with minimal charge injection and on-resistance variation. IC Role / Device Role / Timing Role: CD4007UBMT is wired as bilateral transmission gates using complementary FETs per channel, controlled by CMOS-level logic. Use Value: Delivers <10 Ω on-resistance flatness across 0–5 V signal range and <1 pC charge injection - suitable for 12-bit data acquisition. |
Use Scenario: Implementing custom combinational logic (e.g., XOR, AOI) or state elements in space-constrained embedded controllers where standard logic ICs are unavailable. IC Role / Device Role / Timing Role: CD4007UBMT acts as reconfigurable gate array - its inverter and complementary pairs synthesize NAND/NOR with user-wired pull-up/pull-down networks. Use Value: Reduces PCB footprint vs. discrete transistor logic and avoids ASIC development cost for low-volume, field-programmable functions. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar complementary MOSFET array applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| CD4007UBM96 | Same die, SOIC-14 tape-and-reel packaging (2500 pcs/reel), RoHS-compliant NiPdAu lead finish, MSL Level-1 rating. | Preferred for automated SMT assembly; supports full reflow compatibility and traceable lot control. | Select CD4007UBM96 for volume production with pick-and-place lines; CD4007UBMT is obsolete but may remain in legacy inventory. |
| MC14007UBDR2G | Onsemi variant with identical pinout and electrical specs; wider VDD tolerance (3–18 V), same -55°C to +125°C rating, Pb-free and RoHS compliant. | Drop-in replacement with enhanced long-term availability and automotive qualification support (AEC-Q100 Grade 3). | Choose MC14007UBDR2G for new designs requiring assured supply continuity and automotive-grade reliability documentation. |
Compared with CD4007UBMT, CD4007UBM96 offers modern packaging logistics for SMT lines, while MC14007UBDR2G delivers guaranteed long-term sourcing and AEC-Q100 compliance - both retain identical circuit functionality and pinout, making them direct functional alternatives despite CD4007UBMT's obsolescence status.
Availability
CD4007UBMT is available at Aetrix Electronics and suitable for analog prototyping, discrete circuit emulation, and educational electronics labs requiring stable component supply and legacy design support.
Supply support for CD4007UBMT includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and high-reliability silicon solutions for industrial, automotive, and aerospace markets.
The CD4007UB series belongs to TI's legacy CMOS logic portfolio, designed specifically to provide engineers with configurable, matched transistor arrays for analog circuit experimentation and discrete-level design flexibility.
FAQ
What is the primary function of the CD4007UBMT?
The CD4007UBMT is a configurable CMOS transistor array containing three matched N-channel and three matched P-channel MOSFETs. It is not a logic gate IC but a building-block device used to construct custom current mirrors, differential pairs, analog switches, and inverters by externally wiring its 14 pins. Its value lies in on-die transistor matching and dual-polarity integration - essential for precision analog prototyping where discrete FET selection and layout matching would otherwise dominate design effort. The CD4007UBMT enables rapid implementation of these functions without external matching components.
Is CD4007UBMT pin-compatible with other CD4007 variants like CD4007UBE or CD4007UBM96?
Yes, CD4007UBMT shares identical pinout, terminal functions, and electrical specifications with all CD4007UB family members including CD4007UBE (PDIP), CD4007UBF3A (CDIP), and CD4007UBM96 (SOIC). The only differences are package type (SOIC), packaging format (tube vs. tape-and-reel), and RoHS compliance status. All variants use the same die and internal topology, so circuit designs developed for CD4007UBMT will operate identically when substituted with CD4007UBM96 or CD4007UBE - provided mechanical constraints and assembly methods are addressed.
Why is CD4007UBMT marked as Obsolete, and what does that mean for my design?
CD4007UBMT is marked Obsolete by Texas Instruments due to discontinuation of its specific SOIC tube-packaged variant (SPQ = -, no carrier specified), though the underlying CD4007UB silicon remains actively produced in tape-and-reel formats like CD4007UBM96. For existing designs, CD4007UBMT can still be sourced through authorized distributors' legacy inventories. For new designs, TI recommends migrating to CD4007UBM96 or MC14007UBDR2G to ensure long-term supply, RoHS compliance, and full manufacturing support - the CD4007UBMT itself retains full functional equivalence.
Can CD4007UBMT be used in analog switch applications, and what are its key limitations?
Yes, CD4007UBMT is widely used to implement bilateral analog switches by connecting complementary N- and P-channel FETs as transmission gates. Its key advantages include matched on-resistance (<10 Ω typical), low charge injection (<1 pC), and rail-to-rail signal handling (0 V to VDD). Limitations include maximum signal voltage constrained to VDD – 0.5 V (due to body diode conduction), lack of integrated break-before-make control, and no guaranteed RON flatness above 100 kHz. For CD4007UBMT, optimal analog switching performance occurs below 10 kHz with VDD ≥ 9 V to minimize distortion and crosstalk.
Does CD4007UBMT require external pull-up or pull-down resistors for reliable operation?
No, CD4007UBMT does not require external pull-up or pull-down resistors for basic inverter or current mirror operation because its internal complementary FET structure provides active pull-up (P-channel) and pull-down (N-channel) paths. However, when configuring open-drain or open-source topologies - such as current sources or level translators - external resistors are necessary to define operating point or set gain. In those cases, resistor values must be selected based on CD4007UBMT's output impedance and desired current, typically ranging from 10 kΩ to 1 MΩ depending on speed and power trade-offs.
CD4007UBMT Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- 4000B
- Package/Case:
- 14-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Logic Type:
- Complementary Pair Plus Inverter
- Supply Voltage:
- 3V ~ 18V
- Number of Bits:
- 3
- Operating Temperature:
- -55°C ~ 125°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 14-SOIC
CD4007UBMT FAQ
1.How can I place an order for CD4007UBMT through Aetrix?
Please submit a Request for Quotation (RFQ) for CD4007UBMT on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for CD4007UBMT reliable?
The price and inventory of CD4007UBMT are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for CD4007UBMT is usually 5 days.
3.What payment methods are accepted for CD4007UBMT?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for CD4007UBMT transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for CD4007UBMT?
CD4007UBMT orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your CD4007UBMT order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for CD4007UBMT?
For technical support, including CD4007UBMT datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your CD4007UBMT requirements.
6.How does Aetrix verify that CD4007UBMT is sourced from the original manufacturer or authorized distributors?
All CD4007UBMT products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that CD4007UBMT meets industry standards.
7.What is the process for return or replacement of CD4007UBMT?
All CD4007UBMT units undergo pre-shipment inspection (PSI). If there is an issue with CD4007UBMT, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The CD4007UBMT part is unused and in its original packaging.
Return procedure for CD4007UBMT:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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