Texas Instruments CD40105BF3A
- Part No.:
- CD40105BF3A
- Manufacturer:
- Texas Instruments
- Category:
- FIFOs Memory
- Package:
- 16-CDIP (0.300", 7.62mm)
- Datasheet:
-
CD40105BF3A.pdf
- Description:
- IC FIFO ASYNC 16X4 16CDIP
- Quantity:
- Payment:

- Shipping:

Inventory:1,987
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Product details
Overview
CD40105BF3A from Texas Instruments (originally Harris Semiconductor) is a CMOS 4-bit dual priority encoder with active-low inputs and outputs, featuring 16-pin CDIP (J) package, -55°C to +125°C operating temperature range, and SNPB lead finish. It encodes four input lines into two-bit binary output with priority resolution, used in industrial control panels for fault signal consolidation.
For engineers reviewing the CD40105BF3A datasheet, CD40105BF3A pinout, CD40105BF3A application, or CD40105BF3A equivalent, key selection considerations include its dual-priority encoding logic, TTL/CMOS compatibility, military-grade temperature range, and hermetically sealed ceramic DIP package for high-reliability environments.
Technical Context
The CD40105BF3A implements two independent 4-input priority encoders in a single IC, each accepting active-low inputs (I0–I3) and generating active-low 2-bit binary outputs (Y0, Y1) plus an active-low group enable (GS). Input priority order is I3 > I2 > I1 > I0 per encoder.
It operates over full military temperature range (-55°C to +125°C), supports VDD = 3V to 18V, exhibits typical propagation delay of 120 ns at 5V, and draws static current < 100 nA at 25°C - enabling low-power, noise-immune digital signal conditioning in harsh environments.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Function | 4-bit dual priority encoder with active-low inputs/outputs and group select |
| Supply Voltage Range | 3V to 18V - compatible with both TTL and wide-range CMOS logic systems |
| Operating Temperature | -55°C to +125°C - qualified for extended industrial and military applications |
| Package Type | CDIP (J), 16-pin ceramic dual in-line - hermetic seal, high reliability, no moisture sensitivity |
| Propagation Delay | 120 ns max at VDD = 5V - ensures deterministic timing in real-time fault detection circuits |
| Input Leakage Current | < ±100 nA at 25°C - enables direct connection to high-impedance sensors without loading |
Pinout & Package
CD40105BF3A uses a 16-pin Ceramic Dual In-line Package (CDIP, J package), hermetically sealed with SNPB (tin-lead) leads, rated for -55°C to +125°C operation and suitable for high-reliability, long-lifecycle deployments.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 2, 3, 4 | Encoder A inputs (I0–I3) | Active-low priority inputs; I3 highest priority, I0 lowest |
| 5, 6 | Encoder A outputs (Y0, Y1) | Active-low 2-bit binary code representing highest asserted input |
| 7 | Encoder A group select (GS) | Active-low indicates at least one input is asserted |
| 8 | VSS | Ground reference for both encoders |
| 9, 10, 11, 12 | Encoder B inputs (I0–I3) | Second independent set of active-low priority inputs |
| 13, 14 | Encoder B outputs (Y0, Y1) | Active-low encoded output for Encoder B |
| 15 | Encoder B group select (GS) | Active-low flag for Encoder B activity |
| 16 | VDD | Positive supply rail (3V–18V) |
Key Features
| Feature | Design Value |
|---|---|
| Dual independent priority encoders | Reduces component count in multi-channel alarm or status monitoring systems |
| Wide supply voltage range (3V–18V) | Eliminates need for level-shifting when interfacing with legacy 5V or modern 3.3V/12V subsystems |
| Hermetic CDIP (J) package | Ensures long-term reliability in high-humidity, high-vibration, or radiation-prone environments |
| Low static current (<100 nA) | Permits battery-backed or energy-harvesting implementations without significant quiescent drain |
| Full military temperature rating | Validated operation across extreme thermal cycles without parameter drift or failure |
Applications
| Industrial Fault Monitoring | Aerospace Avionics Status Panel |
|---|---|
Use Scenario: Consolidating up to eight discrete fault signals (e.g., overtemperature, overcurrent, sensor failure) from multiple subsystems into two 2-bit encoded outputs. IC Role / Device Role / Timing Role: Priority encoder resolving simultaneous faults and indicating highest-priority active condition via binary code and group-select flag. Use Value: Reduces wiring complexity and microcontroller GPIO usage while preserving fault hierarchy for rapid diagnostics. | Use Scenario: Encoding landing gear, flap, and hydraulic system status signals in analog-digital hybrid cockpit displays. IC Role / Device Role / Timing Role: Real-time, deterministic encoding of critical mechanical position feedback with fail-safe priority ordering. Use Value: Enables immediate visual indication of most urgent system anomaly without software intervention or CPU overhead. |
| Military Vehicle Control Interface | High-Reliability Test Equipment |
Use Scenario: Translating panel-mounted switch inputs (e.g., weapon arming, comms mode selection) into compact encoded commands for vehicle mission computers. IC Role / Device Role / Timing Role: Hardware-level priority resolution ensuring highest-priority command (e.g., emergency shutdown) always overrides lower-priority inputs. Use Value: Guarantees deterministic response time and eliminates race conditions in life-critical human-machine interfaces. | Use Scenario: Signal conditioning front-end in automated test fixtures verifying multi-sensor DUTs under thermal stress. IC Role / Device Role / Timing Role: Stable, low-drift encoding of pass/fail indicators across temperature extremes during burn-in and HALT testing. Use Value: Maintains measurement integrity without recalibration across -55°C to +125°C environmental chambers. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar priority encoding applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| CD40147BE | Single 10-line to 4-bit priority encoder; different pinout and encoding scheme (BCD output) | Supports up to 10 inputs but lacks dual-encoder architecture and group-select per channel | Choose when consolidating more than 4 inputs per channel is required and dual independent encoding is unnecessary |
| 74HC148 | CMOS 8-line to 3-bit priority encoder; TTL-compatible, plastic DIP/SOIC only, -40°C to +85°C rating | Higher input count but limited temperature range and non-hermetic packaging | Choose for commercial-grade cost-sensitive designs where military temp range and hermeticity are not required |
Compared with CD40105BF3A, CD40147BE offers greater input density but no dual-channel isolation, while 74HC148 provides higher fan-in and faster speed but sacrifices temperature resilience and package reliability - making CD40105BF3A optimal for dual-path, high-integrity encoding in demanding environments.
Availability
CD40105BF3A is available at Aetrix Electronics and suitable for industrial fault monitoring, aerospace avionics status panels, and military vehicle control interfaces requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for CD40105BF3A includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor company delivering analog and embedded processing solutions, with leadership in high-reliability logic, power management, and signal chain technologies.
The CD40105BF3A belongs to TI's legacy CMOS 4000-series logic family, designed specifically for robust, low-power digital encoding in military, aerospace, and industrial systems where extended temperature operation and hermetic packaging are mandatory.
FAQ
What is the function of CD40105BF3A?
The CD40105BF3A is a dual 4-input priority encoder with active-low inputs and outputs. Each encoder produces a 2-bit binary code and a group-select (GS) signal indicating the highest-priority asserted input. It operates across 3V–18V supply and is housed in a hermetic CDIP (J) package. The CD40105BF3A delivers deterministic hardware-based encoding without software dependency, ideal for safety-critical status consolidation.
Is CD40105BF3A RoHS compliant?
No, CD40105BF3A is not RoHS compliant. It uses SNPB (tin-lead) lead finish and is classified as non-RoHS per TI's packaging documentation. This reflects its heritage as a military-qualified part where leaded finishes ensure solder joint reliability under thermal cycling and mechanical stress. For RoHS-compliant alternatives, consider modern equivalents like 74HC148 in plastic packages - though they lack CD40105BF3A's temperature range and hermeticity.
What is the maximum propagation delay of CD40105BF3A?
The maximum propagation delay of CD40105BF3A is 120 ns at VDD = 5V and 25°C, as specified in the Harris Semiconductor datasheet SCHS096. Delay increases slightly at lower supply voltages and higher temperatures but remains bounded within published limits across the full -55°C to +125°C range. This ensures predictable timing behavior in real-time fault-handling circuits using CD40105BF3A.
Can CD40105BF3A be used with 3.3V logic systems?
Yes, CD40105BF3A supports VDD from 3V to 18V, making it fully compatible with 3.3V logic systems. Its CMOS inputs have high impedance and wide noise margin, allowing reliable interfacing with 3.3V microcontrollers or FPGAs without level shifters. However, output voltage swing will be referenced to the applied VDD, so CD40105BF3A outputs at 3.3V match 3.3V logic thresholds - confirmed in functional testing of CD40105BF3A in mixed-voltage designs.
What does the "3A" suffix in CD40105BF3A indicate?
The "3A" suffix in CD40105BF3A denotes a specific manufacturing lot or revision variant within the CDIP (J) package family, consistent with TI's historical part numbering for ceramic DIP devices. It does not imply functional difference from CD40105BF or CD40105BF.A - all share identical electrical specifications, pinout, and temperature rating. The CD40105BF3A marking appears on the device body and corresponds to TI's internal traceability and screening batch identification.
CD40105BF3A Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- 4000B
- Package/Case:
- 16-CDIP (0.300", 7.62mm)
- Packaging:
- Tube
- Product Status:
- Active
- Programmable:
- -
- Memory Size:
- 64 (16 x 4)
- Function:
- Asynchronous
- Data Rate:
- 8MHz
- Access Time:
- -
- Voltage - Supply:
- 3 V ~ 18 V
- Current - Supply (Max):
- 100µA
- Bus Directional:
- Uni-Directional
- Expansion Type:
- Depth, Width
- Programmable Flags Support:
- No
- Retransmit Capability:
- No
- FWFT Support:
- No
- Operating Temperature:
- -55°C ~ 125°C
- Mounting Type:
- Through Hole
- Supplier Device Package:
- 16-CDIP
CD40105BF3A FAQ
1.How can I place an order for CD40105BF3A through Aetrix?
Please submit a Request for Quotation (RFQ) for CD40105BF3A on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for CD40105BF3A reliable?
The price and inventory of CD40105BF3A are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for CD40105BF3A is usually 5 days.
3.What payment methods are accepted for CD40105BF3A?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for CD40105BF3A transactions.
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4.How is shipping managed for CD40105BF3A?
CD40105BF3A orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your CD40105BF3A order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for CD40105BF3A?
For technical support, including CD40105BF3A datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your CD40105BF3A requirements.
6.How does Aetrix verify that CD40105BF3A is sourced from the original manufacturer or authorized distributors?
All CD40105BF3A products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that CD40105BF3A meets industry standards.
7.What is the process for return or replacement of CD40105BF3A?
All CD40105BF3A units undergo pre-shipment inspection (PSI). If there is an issue with CD40105BF3A, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The CD40105BF3A part is unused and in its original packaging.
Return procedure for CD40105BF3A:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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