Texas Instruments CD4010BMT
- Part No.:
- CD4010BMT
- Manufacturer:
- Texas Instruments
- Package:
- 16-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
CD4010BMT.pdf
- Description:
- IC BUFFER NON-INVERT 18V 16SOIC
- Quantity:
- Payment:

- Shipping:

Inventory:2,159
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Product details
Overview
CD4010BMT from Texas Instruments is a hex non-inverting buffer IC in SOIC-16 package, designed for level-shifting and signal fan-out in CMOS logic systems. It operates over -55°C to +125°C, supports 3–18 V supply, and delivers ±4.2 mA output drive at 5 V with typical propagation delay of 80 ns at 5 V.
For engineers reviewing the CD4010BMT datasheet, CD4010BMT pinout, CD4010BMT application, or CD4010BMT equivalent, this device is selected for robust voltage-level translation, noise-immune digital interfacing, and low-power bus buffering in industrial control, instrumentation, and legacy system upgrades where TTL-to-CMOS compatibility and wide VDD range are critical.
Technical Context
The CD4010BMT implements six independent CMOS non-inverting buffers using silicon-gate enhancement-mode technology. Each buffer features high input impedance (>1012 Ω), rail-to-rail output swing, and symmetrical rise/fall times (typ. 60 ns at 5 V).
It shares the CD4000B family's inherent latch-up immunity and static discharge tolerance (±2 kV HBM), and is fully compatible with CD4000-series timing and logic families-enabling direct replacement of CD4009UB inverters when non-inverting polarity is required.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Logic Function | Hex non-inverting buffer - provides true-level signal replication without inversion, essential for bus drivers and clock distribution. |
| Supply Voltage Range | 3 V to 18 V - enables operation across battery-powered, industrial, and mixed-voltage systems without level shifters. |
| Output Drive (IOH/IOL) | ±4.2 mA at VDD = 5 V - sufficient to drive 10 LS-TTL loads or multiple CMOS inputs without external amplification. |
| Propagation Delay | 80 ns max at VDD = 5 V, CL = 50 pF - ensures timing predictability in synchronous control and data routing applications. |
| Input Leakage Current | ≤100 nA at VDD = 18 V - minimizes power loss and signal degradation in high-impedance sensor interface or standby circuits. |
| Operating Temperature | -55°C to +125°C - certified for extended-range deployment in automotive under-hood, aerospace, and military-grade equipment. |
Pinout & Package
CD4010BMT is housed in a 16-pin SOIC (D) package measuring 10.3 mm × 5.3 mm × 1.75 mm (max height), RoHS-compliant with NiPdAu lead finish and moisture sensitivity level (MSL) 1 (unlimited floor life at ≤30°C/60% RH).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 3, 5, 9, 11, 13 | Input A–F | CMOS-compatible high-impedance inputs accepting 0–VDD logic levels; no pull-up/down required. |
| 2, 4, 6, 10, 12, 14 | Output Y1–Y6 | Full-rail CMOS outputs sourcing/sinking up to ±4.2 mA; capable of driving capacitive loads ≤50 pF directly. |
| 7 | VSS | Ground reference terminal - must be connected to system common ground; serves as return path for all six buffers. |
| 16 | VDD | Positive supply terminal - accepts 3–18 V DC; decoupling capacitor (0.1 µF ceramic) recommended adjacent to pin. |
Key Features
| Feature | Design Value |
|---|---|
| Non-inverting logic architecture | Preserves signal polarity across all six channels - eliminates need for double-inversion in feedback or control loops. |
| Wide supply voltage range | 3–18 V operation allows single-device support of 3.3 V microcontrollers, 5 V peripherals, and 12 V industrial I/O without external regulators. |
| High noise immunity | Input threshold at 50% VDD and >100 mV hysteresis margin ensure reliable switching in electrically noisy environments (e.g., motor drives, relay panels). |
| Low quiescent current | Typ. 1 µA at VDD = 5 V - enables use in always-on monitoring circuits with multi-year battery life. |
Applications
| Industrial PLC I/O Expansion | Legacy System Bus Interface |
|---|---|
Use Scenario: Expanding discrete input/output capacity on programmable logic controller backplanes using 24 V DC field signals. IC Role / Device Role / Timing Role: Level-shifting buffer translating 24 V field logic to 5 V CMOS-compatible levels while providing galvanic isolation via external optocouplers. Use Value: Enables direct connection of high-voltage sensors/actuators to low-voltage logic without dedicated level translators or voltage dividers. | Use Scenario: Interfacing vintage 8-bit microprocessor buses (e.g., Z80, 6502) with modern peripheral ICs requiring clean, low-capacitance signal routing. IC Role / Device Role / Timing Role: Signal fan-out repeater isolating address/data bus lines from loading effects of multiple memory or I/O chips. Use Value: Maintains signal integrity and timing margins by reducing effective bus capacitance and restoring edge slew rates degraded by long traces. |
| Automotive Body Control Module | Test Equipment Signal Conditioning |
Use Scenario: Driving LED indicators and small solenoids in vehicle body control units operating across cold-crank (-18 V) to load-dump (+27 V) transients. IC Role / Device Role / Timing Role: High-voltage-tolerant buffer stage between MCU GPIO and external driver FETs or opto-isolators. Use Value: Survives automotive supply excursions due to 18 V absolute maximum rating and built-in transient suppression via internal clamp diodes. | Use Scenario: Conditioning TTL/CMOS logic signals in automated test equipment where precise edge timing and minimal jitter are required. IC Role / Device Role / Timing Role: Low-jitter, deterministic-delay buffer inserted in clock or trigger paths to synchronize measurement acquisition windows. Use Value: Delivers sub-100 ns propagation delay with <±5 ns unit-to-unit variation - critical for time-domain accuracy in boundary-scan or functional test systems. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar hex non-inverting buffer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| CD4010BM | Same die, SOIC-16 tube packaging (40 pcs/tube) vs. tape-and-reel (250 pcs/reel); identical electrical specs and thermal ratings. | No difference in circuit function or layout - only differs in logistics handling and reflow compatibility (both MSL-1). | Select CD4010BM for prototyping or low-volume hand-soldering; CD4010BMT for automated SMT assembly. |
| MC14010BDR2G | Onsemi variant with same pinout and logic function but tighter propagation delay spec (70 ns max at 5 V) and lower IDD (0.5 µA typ). | Suitable for ultra-low-power or high-speed timing-critical paths where marginal delay reduction improves setup/hold margins. | Choose MC14010BDR2G when optimizing for lowest possible static current or sub-75 ns timing budgets in portable instrumentation. |
Compared with CD4010BM and MC14010BDR2G, the CD4010BMT offers identical core functionality with optimized logistics for high-volume SMT production, superior long-term availability through TI's catalog program, and guaranteed -55°C to +125°C performance without derating.
Availability
CD4010BMT is available at Aetrix Electronics and suitable for industrial automation, automotive electronics, and test equipment requiring stable component supply across extended temperature ranges and long product lifecycles.
Supply support for CD4010BMT includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and logic solutions, with decades of heritage in CMOS logic innovation and industrial-grade reliability.
The CD4000B series-including CD4010BMT-is engineered for ruggedized digital interfacing in harsh environments, emphasizing wide VDD tolerance, ESD resilience, and extended temperature operation over speed-optimized performance.
FAQ
What is the maximum supply voltage rating for CD4010BMT?
The CD4010BMT has an absolute maximum supply voltage (VDD) of 18 V. Operation beyond this value risks permanent damage to the internal CMOS structure. For reliable long-term use, TI specifies 3–18 V as the functional range, with full parametric performance guaranteed across that span. The CD4010BMT maintains its specified propagation delay, drive strength, and input thresholds within this window.
Does CD4010BMT support 3.3 V logic systems?
Yes, CD4010BMT is fully operational at 3.3 V supply. Its CMOS input thresholds scale with VDD, ensuring correct logic interpretation of 3.3 V signals. At 3.3 V, it delivers ±1.5 mA output drive and ~140 ns propagation delay (typ.), making it suitable for interfacing with 3.3 V microcontrollers and FPGAs where voltage translation is needed without additional level shifters.
Is CD4010BMT pin-compatible with CD4009UB?
No, CD4010BMT is not pin-compatible with CD4009UB. While both are 16-pin SOIC devices with identical pin spacing, CD4009UB contains six inverting buffers (pins 1–2, 3–4, 5–6, 9–10, 11–12, 13–14), whereas CD4010BMT contains six non-inverting buffers on the same pin pairs. Swapping them requires logic inversion in the system design - they share footprint but not function.
What is the thermal resistance (θJA) of CD4010BMT in SOIC package?
The junction-to-ambient thermal resistance (θJA) for CD4010BMT in SOIC (D) package is 100°C/W under standard JEDEC JESD51-7 conditions (single-layer board, 1 in² copper pad). This value assumes no internal power dissipation exceeding 100 mW - typical for CD4010BMT under normal logic switching conditions. Derating is not required below 125°C ambient when mounted per TI's recommended land pattern.
Can CD4010BMT drive a 50 pF capacitive load reliably?
Yes, CD4010BMT is characterized to drive up to 50 pF capacitive loads with guaranteed timing performance: propagation delay remains ≤80 ns at VDD = 5 V and CL = 50 pF. Rise/fall times stay within 60 ns (typ.) under this condition. For loads exceeding 50 pF, external series termination or buffer staging is recommended to maintain signal integrity and avoid ringing.
CD4010BMT Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- 4000B
- Package/Case:
- 16-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Discontinued at Digi-Key
- Logic Type:
- Buffer, Non-Inverting
- Number of Elements:
- 6
- Number of Bits per Element:
- 1
- Input Type:
- -
- Output Type:
- Push-Pull
- Current - Output High, Low:
- 3mA, 36mA
- Voltage - Supply:
- 3V ~ 18V
- Operating Temperature:
- -55°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-SOIC
CD4010BMT FAQ
1.How can I place an order for CD4010BMT through Aetrix?
Please submit a Request for Quotation (RFQ) for CD4010BMT on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for CD4010BMT reliable?
The price and inventory of CD4010BMT are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for CD4010BMT is usually 5 days.
3.What payment methods are accepted for CD4010BMT?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for CD4010BMT transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for CD4010BMT?
CD4010BMT orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your CD4010BMT order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for CD4010BMT?
For technical support, including CD4010BMT datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your CD4010BMT requirements.
6.How does Aetrix verify that CD4010BMT is sourced from the original manufacturer or authorized distributors?
All CD4010BMT products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that CD4010BMT meets industry standards.
7.What is the process for return or replacement of CD4010BMT?
All CD4010BMT units undergo pre-shipment inspection (PSI). If there is an issue with CD4010BMT, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The CD4010BMT part is unused and in its original packaging.
Return procedure for CD4010BMT:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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