Texas Instruments CD4013BEE4
- Part No.:
- CD4013BEE4
- Manufacturer:
- Texas Instruments
- Category:
- Flip Flops
- Package:
- 14-DIP (0.300", 7.62mm)
- Datasheet:
-
CD4013BEE4.pdf
- Description:
- IC FF D-TYPE DUAL 1BIT 14DIP
- Quantity:
- Payment:

- Shipping:

Inventory:1,401
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
CD4013BEE4 from Texas Instruments is a CMOS dual D-type flip-flop in 14-pin PDIP package, featuring two independent edge-triggered storage elements with asynchronous set/reset, 3–18 V supply range, and 16 MHz max clock toggle rate at 10 V. It performs data latching, toggle, and shift register functions in power management and industrial control logic circuits.
For engineers reviewing the CD4013BEE4 datasheet, CD4013BEE4 pinout, CD4013BEE4 application, or CD4013BEE4 equivalent, this page delivers verified functional modes, static/dynamic timing specs, package-confirmed pin mapping, and real-world implementation context for reliable selection in safety-critical and wide-temperature designs.
Technical Context
The CD4013BEE4 implements two identical, electrically isolated master-slave D flip-flops, each triggered on the positive-going edge of the clock input. Set and reset are asynchronous, overriding clock and data states with high-level assertion.
It operates across –55°C to +125°C with static current as low as 0.02 µA at 25°C and 5 V, and supports symmetrical output drive (±0.51 mA at 5 V) with noise margins of 1 V (VDD = 5 V), 2 V (VDD = 10 V), and 2.5 V (VDD = 15 V).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Logic Type | Dual D-type positive-edge-triggered flip-flop with independent asynchronous set/reset per channel |
| Supply Voltage Range | 3 V to 18 V - enables direct interface with legacy 5 V, industrial 12 V, and battery-backed 3.3 V systems without level shifting |
| Max Clock Frequency | 16 MHz (typical) at VDD = 10 V - sufficient for medium-speed control sequencing and debounce applications |
| Propagation Delay | 300 ns (max) at VDD = 5 V, CL = 50 pF - defines worst-case timing budget for synchronous state transitions |
| Input Current | ≤ 1 µA at 18 V over full temperature range - ensures minimal loading on driving logic and stable DC biasing |
| Operating Temperature | –55°C to +125°C - validated for aerospace, automotive under-hood, and industrial motor control environments |
| Package | 14-pin PDIP (plastic dual in-line), 19.30 mm × 6.35 mm - compatible with through-hole prototyping, legacy PCBs, and manual rework |
Pinout & Package
CD4013BEE4 uses a 14-pin PDIP (plastic dual in-line) package with 2.54 mm pitch, 19.30 mm × 6.35 mm body size, and through-hole mounting. Pin 7 is VSS (ground), pin 14 is VDD (positive supply), and all inputs include CMOS protection networks.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 2 | Q1 / Q1 | Non-inverted and inverted outputs of Channel 1 - provide complementary logic states for differential sensing or reset feedback |
| 3 | CLOCK1 | Positive-edge-triggered clock input for Channel 1 - initiates data transfer from D1 to Q1 only on rising transition |
| 4 | RESET1 | Asynchronous active-high reset for Channel 1 - forces Q1 = 0 and Q1 = 1 independent of clock or data |
| 5 | D1 | Data input for Channel 1 - sampled at CLOCK1 rising edge and latched to Q1 if RESET1 and SET1 are low |
| 6 | SET1 | Asynchronous active-high set for Channel 1 - forces Q1 = 1 and Q1 = 0 independent of clock or data |
| 7 | VSS | Ground reference terminal - must be connected to system common ground with low-impedance path to minimize noise coupling |
| 8 | SET2 | Asynchronous active-high set for Channel 2 - functionally identical to SET1 but isolated to Channel 2 |
| 9 | D2 | Data input for Channel 2 - operates independently of Channel 1 with dedicated clock, set, and reset |
| 10 | RESET2 | Asynchronous active-high reset for Channel 2 - forces Q2 = 0 and Q2 = 1 regardless of other inputs |
| 11 | CLOCK2 | Positive-edge-triggered clock input for Channel 2 - enables independent timing control for dual-channel operation |
| 12, 13 | Q2 / Q2 | Non-inverted and inverted outputs of Channel 2 - support independent status monitoring or cascaded logic stages |
| 14 | VDD | Positive supply terminal - accepts 3–18 V DC; requires local 0.1 µF bypass capacitor to suppress switching transients |
Key Features
| Feature | Design Value |
|---|---|
| Asynchronous Set-Reset | Independent high-level assertion on SET/RESET pins forces immediate Q/Q output states without clock dependency - critical for emergency shutdown or initialization |
| Wide Supply Range | 3 V to 18 V operation - eliminates need for external voltage regulators in mixed-supply systems and extends battery life in portable equipment |
| Low Quiescent Current | ≤ 0.02 µA at 25°C and 5 V - reduces standby power in always-on monitoring circuits and energy-sensitive IoT nodes |
| High Noise Immunity | 2.5 V noise margin at VDD = 15 V - prevents false triggering in electrically noisy industrial environments with motor drives or relay switching |
| Temperature Robustness | Specified from –55°C to +125°C - supports deployment in automotive engine compartments, outdoor telecom gear, and military-grade hardware |
Applications
| Power Button Debounce | Two-Phase Clock Divider |
|---|---|
|
Use Scenario: Mechanical push-button switch interfacing with microcontroller GPIO, where contact bounce causes multiple unintended interrupts. IC Role / Device Role / Timing Role: CD4013BEE4 acts as a synchronous edge-triggered latch, using one flip-flop to sample button state on a clean system clock edge and suppress chatter. Use Value: Eliminates software debouncing overhead and guarantees single-interrupt behavior even under 10 ms bounce duration - improves MCU responsiveness and firmware reliability. |
Use Scenario: Generating non-overlapping clock phases for bidirectional bus control or H-bridge gate driving in motor drivers. IC Role / Device Role / Timing Role: CD4013BEE4 configured as a toggle flip-flop (Q→D feedback) divides input clock by two; second stage provides 90° phase-shifted output via delayed propagation. Use Value: Produces precise 50% duty-cycle, phase-controlled clocks without external PLLs or delay lines - reduces BOM count and layout complexity. |
| Industrial Status Latch | Legacy System Data Hold |
|
Use Scenario: Capturing and holding fault conditions (e.g., overtemperature, overcurrent) in PLC I/O modules until acknowledged by host controller. IC Role / Device Role / Timing Role: CD4013BEE4 stores alarm state using SET input driven by comparator output; RESET is controlled by host command pulse. Use Value: Maintains fault visibility across power cycles and communication gaps - ensures no critical event is lost during transient network outages. |
Use Scenario: Interfacing modern microcontrollers with legacy parallel-data peripherals (e.g., EPROMs, DACs) requiring stable address/data hold during bus arbitration. IC Role / Device Role / Timing Role: CD4013BEE4 latches address bits using system clock edge, holding valid levels while CPU executes other instructions. Use Value: Enables seamless integration of new controllers with older memory-mapped devices without redesigning timing-critical glue logic. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual D-type flip-flop applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| CD4013BM | SOIC-14 surface-mount package; identical electrical specs and pinout; rated for same –55°C to +125°C range | Required for automated SMT assembly; unsuitable for hand-soldered prototypes or through-hole boards | Select CD4013BM when board space is constrained and reflow capability exists; CD4013BEE4 remains optimal for breadboarding and repairability. |
| MC14013BDR2G | Onsemi variant with same logic function and 3–18 V range; slightly higher max IDD (2 µA at 25°C vs. 0.02 µA); identical pinout | Validated for automotive AEC-Q100 Grade 3 (–40°C to +85°C); not rated for extended –55°C operation | Choose MC14013BDR2G only for cost-sensitive commercial applications within standard temp range; CD4013BEE4 preferred for extended temperature or low-power priority. |
Compared with CD4013BM and MC14013BDR2G, the CD4013BEE4 offers superior low-power performance (0.02 µA quiescent current), full military-grade temperature coverage (–55°C to +125°C), and through-hole compatibility - making it the most robust choice for prototyping, field-repairable systems, and harsh-environment deployments.
Availability
CD4013BEE4 is available at Aetrix Electronics and suitable for industrial control panels, power management subsystems, and legacy system upgrades requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for CD4013BEE4 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and logic ICs, with decades of expertise in radiation-tolerant and high-reliability CMOS design.
The CD4013BEE4 belongs to TI's CD4000B series of buffered CMOS logic devices, engineered for wide-voltage operation, low power consumption, and robust noise immunity in industrial, aerospace, and medical instrumentation.
FAQ
What is the maximum clock frequency supported by CD4013BEE4?
The CD4013BEE4 supports a maximum clock input frequency of 16 MHz (typical) at VDD = 10 V, and up to 24 MHz (typical) at VDD = 15 V. At 5 V supply, the typical maximum is 7 MHz. These values assume CL = 50 pF and TA = 25°C; derating applies at temperature extremes or higher capacitive loads. The CD4013BEE4 datasheet specifies fCL min/max across voltage and temperature conditions.
Does CD4013BEE4 support asynchronous reset functionality?
Yes, CD4013BEE4 provides true asynchronous reset: asserting a high logic level on RESET1 or RESET2 immediately forces the corresponding Q output low and Q output high, regardless of clock state or data input. This behavior is confirmed in the device functional table and timing diagrams of the official CD4013B datasheet (SCHS023E).
What is the operating temperature range for CD4013BEE4?
The CD4013BEE4 is specified for continuous operation from –55°C to +125°C, validated across all electrical parameters in the datasheet. This extended range is explicitly listed in the Recommended Operating Conditions table and Thermal Information section, confirming suitability for automotive under-hood, industrial motor control, and aerospace applications.
Can CD4013BEE4 be used with a 3.3 V supply?
Yes, CD4013BEE4 operates reliably down to 3 V supply voltage, as stated in the Recommended Operating Conditions table. At 3.3 V, it maintains full logic functionality with reduced speed (fCL ≈ 3.5 MHz typical) and increased propagation delay, but retains noise margin and static current advantages essential for low-power embedded systems.
Is CD4013BEE4 pin-compatible with other CD4013 variants?
Yes, CD4013BEE4 shares identical pinout and logic function with all CD4013B family members including CD4013BM (SOIC), CD4013BPW (TSSOP), and CD4013BF (CDIP). Pin numbering, signal names, and electrical behavior are standardized across packages - enabling direct substitution where mechanical fit permits.
CD4013BEE4 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- 4000B
- Package/Case:
- 14-DIP (0.300", 7.62mm)
- Packaging:
- Tube
- Product Status:
- Discontinued at Digi-Key
- Function:
- Set(Preset) and Reset
- Type:
- D-Type
- Output Type:
- Complementary
- Number of Elements:
- 2
- Number of Bits per Element:
- 1
- Clock Frequency:
- 24 MHz
- Max Propagation Delay @ V, Max CL:
- 90ns @ 15V, 50pF
- Trigger Type:
- Positive Edge
- Current - Output High, Low:
- 6.8mA, 6.8mA
- Voltage - Supply:
- 3V ~ 18V
- Current - Quiescent (Iq):
- 4 µA
- Input Capacitance:
- 5 pF
- Operating Temperature:
- -55°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Through Hole
- Supplier Device Package:
- 14-PDIP
CD4013BEE4 FAQ
1.How can I place an order for CD4013BEE4 through Aetrix?
Please submit a Request for Quotation (RFQ) for CD4013BEE4 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for CD4013BEE4 reliable?
The price and inventory of CD4013BEE4 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for CD4013BEE4 is usually 5 days.
3.What payment methods are accepted for CD4013BEE4?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for CD4013BEE4 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for CD4013BEE4?
CD4013BEE4 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your CD4013BEE4 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for CD4013BEE4?
For technical support, including CD4013BEE4 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your CD4013BEE4 requirements.
6.How does Aetrix verify that CD4013BEE4 is sourced from the original manufacturer or authorized distributors?
All CD4013BEE4 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that CD4013BEE4 meets industry standards.
7.What is the process for return or replacement of CD4013BEE4?
All CD4013BEE4 units undergo pre-shipment inspection (PSI). If there is an issue with CD4013BEE4, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The CD4013BEE4 part is unused and in its original packaging.
Return procedure for CD4013BEE4:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
CD4013BEE4 Tags
-
SN74HC74DR
Texas Instruments

-
SN74HC74PWR
Texas Instruments

-
74LVC1G74GT,115
Nexperia USA Inc.

-
SN74LVC2G74DCUR
Texas Instruments
-
CD4013BM96
Texas Instruments

-
SN74HCT273PWR
Texas Instruments

-
SN74LVC1G74DCUR
Texas Instruments

-
SN74HC574DWR
Texas Instruments
-
74LVC1G74DC,125
Nexperia USA Inc.

-
SN74HC273DWR
Texas Instruments

-
SN74HCT574DWR
Texas Instruments

-
SN74LVC1G74DCTR
Texas Instruments
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

