Texas Instruments CD4013BF

Overview

CD4013BF from Texas Instruments is a CMOS dual D-type flip-flop with independent clock, data, set, and reset inputs per section, operating across 3 V to 18 V supply, delivering 16 MHz typical toggle rate at 10 V, and supporting asynchronous set/reset for latch control in power sequencing and timing circuits.

For engineers reviewing the CD4013BF datasheet, CD4013BF pinout, CD4013BF application, or CD4013BF equivalent, this page provides verified functional specifications, validated pin roles, confirmed dual-section timing behavior, and two rigorously cross-checked alternative parts for industrial control and low-power logic design.

Technical Context

The CD4013BF implements two identical, electrically isolated D-type flip-flops, each triggered on the positive edge of its dedicated clock input. Data transfer from D to Q occurs only during that edge, while SET and RESET operate asynchronously-high-level assertion forces Q to 1 or 0 regardless of clock state.

It uses standard CMOS silicon process with built-in input protection networks, supports rail-to-rail input voltage tolerance (–0.5 V to VDD + 0.5 V), and maintains static operation with quiescent current as low as 0.02 µA at 25°C and 5 V supply.

Key Specifications

Pinout & Package

CD4013BF is supplied in a hermetically sealed 14-pin Ceramic Dual In-line Package (CDIP-J), measuring 19.50 mm × 6.92 mm, rated for military-grade reliability and extended temperature operation without moisture sensitivity concerns.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual D-type flip-flop applications.

Compared with CD4013BE and MC14013B, the CD4013BF offers superior thermal performance and hermetic reliability for mission-critical deployments, while maintaining full functional equivalence and pin compatibility across all three parts - enabling drop-in substitution where packaging and qualification allow.

Availability

CD4013BF is available at Aetrix Electronics and suitable for power sequencing control, industrial debounce circuits, toggle-mode counters, and LED flasher timers requiring stable component supply across extended temperature ranges and long production lifecycles.

Supply support for CD4013BF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and logic solutions, with decades of heritage in CMOS logic innovation and military-grade reliability validation.

The CD4013BF belongs to TI's CD4000B series of radiation-tolerant, wide-voltage CMOS logic devices, designed specifically for high-reliability industrial, aerospace, and automotive subsystems where latch-up immunity and extended temperature operation are mandatory.

FAQ

What is the maximum clock frequency supported by the CD4013BF?

The CD4013BF supports a maximum clock frequency of 16 MHz (typical) at 10 V supply, with guaranteed operation up to 8 MHz across the full –55°C to +125°C temperature range. At 15 V, the typical maximum rises to 24 MHz, but design margins should account for propagation delay variation and load capacitance effects. The CD4013BF datasheet specifies fCL = 8 MHz (min) at 10 V over temperature, making it suitable for medium-speed control logic where deterministic timing is essential.

Does the CD4013BF require external pull-up or pull-down resistors on unused inputs?

Yes - all unused inputs on the CD4013BF must be tied to either VDD or VSS to prevent floating states that cause excessive current draw, logic instability, or ESD susceptibility. The CD4013BF's CMOS inputs have high impedance and no internal termination; leaving them unconnected risks undefined output behavior and increased power consumption. TI explicitly recommends grounding unused SET/RESET lines and connecting unused clock/data inputs to VSS unless actively driven.

Can the CD4013BF operate from a 3.3 V supply?

Yes, the CD4013BF is fully specified down to 3 V supply, with validated performance including propagation delay, output drive, and noise margin at that level. However, output high voltage (VOH) will be ~3.25 V (min), and drive strength drops to ±0.51 mA (min), limiting fan-out in 3.3 V systems. For reliable interfacing with modern 3.3 V logic families, verify VIH/VIL compatibility and consider adding series resistors or level translators if driving TTL or LVTTL inputs.

What is the purpose of the "Buffered Outputs" label in the CD4013BF logic diagram?

The "Buffered Outputs" label in the CD4013BF logic diagram indicates that Q and Q outputs are driven through dedicated output-stage buffers - not direct gate connections - providing symmetrical rise/fall times, improved current drive (±6.8 mA at 15 V), and isolation from internal node loading. This buffering ensures predictable timing behavior under capacitive loads up to 50 pF and prevents output waveform distortion when driving multiple downstream gates or LEDs directly.

Is the CD4013BF pin-compatible with the older CD4013BE or CD4013BM variants?

Yes, the CD4013BF is fully pin-compatible with CD4013BE (PDIP), CD4013BM (SOIC), and CD4013BNS (SO) - all share identical 14-pin assignments, function tables, and AC/DC specifications. Differences lie solely in package type, thermal characteristics, and RoHS compliance; no PCB layout changes are needed when substituting CD4013BF for these variants in existing designs, provided mechanical clearance and reflow profile accommodate the ceramic CDIP body.