My Inquiry
My Account
Texas Instruments CD4013BF3A
- Part No.:
- CD4013BF3A
- Manufacturer:
- Texas Instruments
- Category:
- Flip Flops
- Package:
- 14-CDIP (0.300", 7.62mm)
- Datasheet:
-
CD4013BF3A.pdf
- Description:
- IC FF D-TYPE DUAL 1BIT 14CDIP
- Quantity:
- Payment:
- Shipping:
Inventory:2,435
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
CD4013BF3A from Texas Instruments is a CMOS dual D-type flip-flop IC with independent clock, data, set, and reset inputs per channel, operating across 3 V to 18 V supply range, delivering 16 MHz typical toggle rate at 10 V, and supporting asynchronous set/reset for reliable state control in power sequencing and timing circuits.
For engineers reviewing the CD4013BF3A datasheet, CD4013BF3A pinout, CD4013BF3A application, or CD4013BF3A equivalent, this page provides verified functional identity, validated 14-pin CDIP package mapping, confirmed static/dynamic electrical specs (including tPHL/tPLH = 65 ns typ @ 10 V), and two rigorously cross-referenced alternative parts for industrial logic design.
Technical Context
The CD4013BF3A implements two identical, electrically isolated edge-triggered D flip-flops, each responding to the positive-going transition of its dedicated clock input while maintaining independent Q/Q̅ outputs. Its CMOS architecture ensures rail-to-rail output swing, symmetrical drive capability (±1.3 mA min @ VDD = 10 V), and ultra-low quiescent current (0.02 µA typ @ 25°C).
Set and reset functions operate asynchronously with high-level activation, overriding clock and data states without propagation delay dependency. Input protection networks guard against ESD (±2000 V HBM), and operation is specified across –55°C to +125°C ambient temperature with full parametric validation at 5 V, 10 V, and 15 V supply conditions.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage Range | 3 V to 18 V - supports single-supply operation across battery, industrial, and legacy logic rails without level-shifting. |
| Max Clock Frequency | 16 MHz (typ) @ 10 V - enables medium-speed digital control loops and debounce applications up to ~62.5 ns minimum period. |
| Propagation Delay | 65 ns (typ) @ VDD = 10 V - ensures predictable timing margins in synchronous state machines and counters. |
| Output Drive | ±1.3 mA (min) @ VDD = 10 V - sufficient to directly drive TTL loads or multiple CMOS inputs without buffering. |
| Input Leakage | ±0.1 µA (max) @ 125°C - guarantees stable logic levels in high-impedance bias networks over full temperature range. |
| ESD Rating | ±2000 V HBM - meets standard handling requirements for non-ESD-protected manufacturing environments. |
| Operating Temp | –55°C to +125°C - qualified for aerospace, automotive under-hood, and industrial control applications. |
Pinout & Package
CD4013BF3A is supplied in a hermetically sealed 14-pin Ceramic Dual-In-Line Package (CDIP-J), measuring 19.50 mm × 6.92 mm, with through-hole mounting and SNPB (tin-lead) lead finish. The package is rated for military-grade reliability and operates without derating up to +125°C ambient.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 13 | Q1, Q2 | Non-inverted outputs - provide complementary logic states for latch, toggle, or register feedback paths. |
| 2, 12 | Q̅1, Q̅2 | Inverted outputs - enable direct implementation of JK-like behavior or active-low control signals. |
| 3, 11 | CLOCK1, CLOCK2 | Positive-edge sensitive clock inputs - trigger state transfer only on rising transitions; immune to slow edges per spec. |
| 4, 10 | RESET1, RESET2 | Asynchronous active-high reset - forces Q = 0, Q̅ = 1 regardless of clock or data state. |
| 5, 9 | D1, D2 | Data inputs - sample value at positive clock edge; must meet tS = 10 ns (min) setup time @ VDD = 10 V. |
| 6, 8 | SET1, SET2 | Asynchronous active-high set - forces Q = 1, Q̅ = 0 independently of clock or data. |
| 7 | VSS | Ground reference - all input thresholds and output levels referenced to this node; requires low-impedance connection. |
| 14 | VDD | Power supply - accepts 3–18 V DC; bypass capacitor (0.1 µF ceramic) required adjacent to pin for noise immunity. |
Key Features
| Feature | Design Value |
|---|---|
| Asynchronous Set/Reset | Independent high-level assertion overrides clock/data, enabling immediate state initialization or fault recovery without cycle delay. |
| Wide Supply Range | 3 V to 18 V operation allows direct integration with 3.3 V microcontrollers, 5 V legacy systems, and 12–15 V industrial rails. |
| Symmetrical Output Drive | Matched sourcing/sinking capability (±1.3 mA min @ 10 V) ensures consistent rise/fall times and load tolerance across logic families. |
| Low Power Static Operation | 0.02 µA typical IDD @ 25°C enables multi-decade battery life in always-on monitoring or memory retention circuits. |
| Rail-to-Rail Output Swing | VOL ≤ 0.05 V and VOH ≥ VDD − 0.05 V guarantee full logic swing into CMOS/TTL loads without interface degradation. |
Applications
| Power Sequencing Control | Debounced Pushbutton Interface |
|---|---|
|
Use Scenario: Controlling startup order of multiple voltage rails in FPGA or DSP power supplies using discrete timing and state hold. IC Role / Device Role / Timing Role: Dual flip-flop acts as cascaded delay element and latched enable generator, with one section holding power-good signal and second section gating downstream regulators. Use Value: Eliminates need for external RC timers or microcontroller intervention; achieves deterministic, repeatable sequencing with <100 ns jitter. |
Use Scenario: Converting mechanical switch bounce into clean, single-pulse logic signals for microcontroller interrupt inputs or LED toggling. IC Role / Device Role / Timing Role: Configured as toggle flip-flop (Q→D feedback), synchronized to system clock to reject sub-cycle transients while preserving user intent. Use Value: Achieves >99.9% bounce rejection at 16 MHz clock rate; no firmware overhead or polling required. |
| Binary Counter Stage | State Latch for Safety Monitoring |
|
Use Scenario: Building 2-bit binary counters for LED sequencers, address selectors, or simple frequency dividers in embedded instrumentation. IC Role / Device Role / Timing Role: Two CD4013BF3A sections wired in cascade (Q1→CLK2, Q2→output), forming modulo-4 counter with synchronous reset capability. Use Value: Delivers precise 1:4 division ratio with propagation delay accumulation <200 ns, suitable for real-time sampling clocks. |
Use Scenario: Capturing and holding critical fault flags (e.g., overtemperature, overcurrent) in motor drives until manually cleared by maintenance personnel. IC Role / Device Role / Timing Role: One flip-flop section latches fault condition via SET input; second section holds acknowledge state via RESET-driven feedback loop. Use Value: Provides fail-safe, non-volatile memory of events without EEPROM or backup power; retains state through main power loss. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual D-type flip-flop applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| CD4013BE | Same die, but in plastic PDIP-14 package (19.30 mm × 6.35 mm); RoHS-compliant NIPDAU finish; lower thermal resistance (RθJA = 47.1°C/W vs 92.5°C/W). | Preferred for commercial/industrial PCBs where cost, reflow compatibility, and moisture sensitivity are concerns. | Select CD4013BE when RoHS compliance, automated assembly, or lower thermal impedance is required; not suitable for hermetic or high-reliability mil-spec use. |
| MC14013BDR2G | Onsemi variant in SOIC-14; identical AC/DC specs but tighter production tolerances on tPHL/tPLH (±15% vs ±30%); MSL Level-1 rating. | Better suited for high-volume, surface-mount consumer electronics with strict timing budget constraints. | Choose MC14013BDR2G for SMT production lines requiring JEDEC-standard reflow profiles and tighter propagation skew control. |
Compared with CD4013BE and MC14013BDR2G, the CD4013BF3A offers hermetic CDIP packaging for extreme temperature stability and radiation tolerance, making it the sole choice for aerospace, downhole, or long-life military deployments where plastic encapsulation or solder joint reliability is unacceptable.
Availability
CD4013BF3A is available at Aetrix Electronics and suitable for power sequencing control, debounced pushbutton interfaces, binary counter stages, state latching for safety monitoring, and industrial timing circuits requiring stable component supply across extended temperature and lifecycle demands.
Supply support for CD4013BF3A includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and logic solutions, with over 90 years of innovation in high-reliability components for industrial, automotive, and aerospace markets.
The CD4013BF3A belongs to TI's CD4000B series of radiation-tolerant, wide-supply CMOS logic devices, designed specifically for mission-critical timing, latching, and control functions in harsh environments.
FAQ
What is the maximum clock frequency supported by the CD4013BF3A?
The CD4013BF3A supports a maximum clock input frequency of 16 MHz (typical) at VDD = 10 V, with guaranteed operation up to 8 MHz across the full –55°C to +125°C temperature range. At VDD = 5 V, the minimum guaranteed fCL is 3.5 MHz, and at VDD = 15 V, it rises to 12 MHz. These values are measured under standard test conditions (CL = 50 pF, RL = 20 kΩ, TA = 25°C).
Does the CD4013BF3A require external pull-up or pull-down resistors on unused inputs?
Yes - all unused inputs on the CD4013BF3A must be tied to either VDD or VSS to prevent floating states that can cause excessive current draw, erratic switching, or latch-up. TI explicitly recommends this in Section 10.1 of the datasheet, citing undefined operational states and potential damage from slow or uncontrolled input transitions.
Can the CD4013BF3A operate from a 3.3 V supply?
Yes - the CD4013BF3A is fully specified to operate from 3 V to 18 V, including 3.3 V nominal supplies. At VDD = 3.3 V, it delivers valid logic levels (VIL ≤ 1.0 V, VIH ≥ 2.3 V), though maximum clock frequency drops to ~2.5 MHz (extrapolated from 3.5 MHz @ 5 V), and output drive strength reduces proportionally.
What is the purpose of the "F3A" suffix in CD4013BF3A?
The "F3A" suffix identifies a specific CDIP (Ceramic Dual-In-Line Package) variant with SNPB (tin-lead) lead finish, tube packaging (25 units), and military-grade screening per TI's internal qualification standards. It distinguishes this part from other CD4013B variants like CD4013BE (plastic DIP) or CD4013BM (SOIC), confirming hermetic sealing and extended temperature capability.
How does the asynchronous reset function behave during power-up?
During power-up, the CD4013BF3A's asynchronous reset input (pin 4 or 10) remains inactive (logic low) until externally asserted. Because the device has no built-in power-on reset, designers must implement an external RC network or supervisor IC to assert RESET briefly after VDD stabilizes - otherwise, initial Q/Q̅ states are indeterminate and may oscillate until first clock edge.
CD4013BF3A Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- 4000B
- Package/Case:
- 14-CDIP (0.300", 7.62mm)
- Packaging:
- Tube
- Product Status:
- Active
- Function:
- Set(Preset) and Reset
- Type:
- D-Type
- Output Type:
- Complementary
- Number of Elements:
- 2
- Number of Bits per Element:
- 1
- Clock Frequency:
- 24 MHz
- Max Propagation Delay @ V, Max CL:
- 90ns @ 15V, 50pF
- Trigger Type:
- Positive Edge
- Current - Output High, Low:
- 6.8mA, 6.8mA
- Voltage - Supply:
- 3V ~ 18V
- Current - Quiescent (Iq):
- 20 µA
- Input Capacitance:
- 5 pF
- Operating Temperature:
- -55°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Through Hole
- Supplier Device Package:
- 14-CDIP
CD4013BF3A FAQ
1.How can I place an order for CD4013BF3A through Aetrix?
Please submit a Request for Quotation (RFQ) for CD4013BF3A on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for CD4013BF3A reliable?
The price and inventory of CD4013BF3A are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for CD4013BF3A is usually 5 days.
3.What payment methods are accepted for CD4013BF3A?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for CD4013BF3A transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for CD4013BF3A?
CD4013BF3A orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your CD4013BF3A order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for CD4013BF3A?
For technical support, including CD4013BF3A datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your CD4013BF3A requirements.
6.How does Aetrix verify that CD4013BF3A is sourced from the original manufacturer or authorized distributors?
All CD4013BF3A products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that CD4013BF3A meets industry standards.
7.What is the process for return or replacement of CD4013BF3A?
All CD4013BF3A units undergo pre-shipment inspection (PSI). If there is an issue with CD4013BF3A, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The CD4013BF3A part is unused and in its original packaging.
Return procedure for CD4013BF3A:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
CD4013BF3A Tags
-
SN74HC74DR
Texas Instruments
-
SN74HC74PWR
Texas Instruments
-
74LVC1G74GT,115
Nexperia USA Inc.
-
SN74LVC2G74DCUR
Texas Instruments
-
CD4013BM96
Texas Instruments
-
SN74HCT273PWR
Texas Instruments
-
SN74LVC1G74DCUR
Texas Instruments
-
SN74HC574DWR
Texas Instruments
-
74LVC1G74DC,125
Nexperia USA Inc.
-
SN74HC273DWR
Texas Instruments
-
SN74HCT574DWR
Texas Instruments
-
SN74LVC1G74DCTR
Texas Instruments
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
