Texas Instruments CD4013BME4
- Part No.:
- CD4013BME4
- Manufacturer:
- Texas Instruments
- Category:
- Flip Flops
- Package:
- 14-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
CD4013BME4.pdf
- Description:
- IC FF D-TYPE DUAL 1BIT 14SOIC
- Quantity:
- Payment:

- Shipping:

Inventory:2,805
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Product details
Overview
CD4013BME4 from Texas Instruments is a CMOS dual D-type flip-flop IC with independent clock, data, set, and reset inputs per channel, Q/Q̅ buffered outputs, 3–18 V supply range, ±1 µA max input current at 18 V, and 16 MHz typical toggle rate at 10 V - used in power button debouncing, divide-by-two clock generation, and shift register stages.
For engineers reviewing the CD4013BME4 datasheet, CD4013BME4 pinout, CD4013BME4 application, or CD4013BME4 equivalent, this page delivers verified functional modes, static/dynamic timing specs, SOIC-14 package details, and real-world implementation guidance for industrial control, medical instrumentation, and grid infrastructure timing circuits.
Technical Context
The CD4013BME4 implements two identical, asynchronous-set/reset, positive-edge-triggered D flip-flops in a single SOIC-14 package. Each section features independent D, CLK, SET, RESET, Q, and Q̅ terminals with symmetrical output drive capability and full rail-to-rail voltage operation (3–18 V).
It operates across –55°C to +125°C, supports static latch behavior, and delivers propagation delays as low as 45 ns (tPHL/tPLH, VDD = 15 V), with setup/hold times down to 7 ns/2 ns respectively - enabling reliable use in medium-speed digital state machines without external synchronization.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage Range | 3 V to 18 V - enables direct interface with legacy 5 V, modern 3.3 V, and high-voltage industrial rails without level-shifting. |
| Max Clock Frequency | 16 MHz (typical at VDD = 10 V) - sufficient for divide-by-two counters, LED blinkers, and basic serial data latching. |
| Propagation Delay | 45–90 ns (tPHL/tPLH, VDD = 15 V) - ensures predictable timing margins in synchronous logic chains with 50 pF load. |
| Input Current | ±0.1 µA max (VDD = 18 V, TA = 25°C) - minimizes loading on upstream drivers and enables high-impedance control signal routing. |
| Output Drive | ±6.8 mA (VDD = 15 V, VO = 13.5 V / 1.5 V) - directly drives LEDs, small relays, or TTL-compatible inputs without buffering. |
| Operating Temperature | –55°C to +125°C - qualified for under-hood automotive, outdoor telecom, and industrial motor control environments. |
| Noise Margin | 2.5 V (VDD = 15 V) - provides robust immunity against supply ripple and crosstalk in noisy mixed-signal PCBs. |
Pinout & Package
CD4013BME4 is housed in a 14-pin SOIC (D) package measuring 8.65 mm × 3.90 mm, with gull-wing leads, RoHS-compliant NiPdAu plating, and moisture sensitivity level 1 (MSL-1, unlimited floor life).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 13 | Q1, Q2 | Non-inverted outputs - drive downstream logic or indicators with standard CMOS voltage levels. |
| 2, 12 | Q̅1, Q̅2 | Inverted complementary outputs - enable differential signaling or eliminate external inverters in toggle configurations. |
| 3, 11 | CLOCK1, CLOCK2 | Positive-edge-triggered clock inputs - sample D-input state only on rising transitions; tolerant of slow edges (5 µs max rise/fall time at VDD = 15 V). |
| 4, 10 | RESET1, RESET2 | Asynchronous active-high reset - forces Q = 0 and Q̅ = 1 independently of clock, critical for power-on initialization. |
| 5, 9 | D1, D2 | Data inputs - sampled on next clock edge; require ≥7 ns setup time (VDD = 15 V) to avoid metastability. |
| 6, 8 | SET1, SET2 | Asynchronous active-high set - forces Q = 1 and Q̅ = 0 regardless of clock or D state, enabling manual override. |
| 7 | VSS | Ground reference - must be low-impedance connection; all internal logic referenced to this node. |
| 14 | VDD | Positive supply rail - bypass with 0.1 µF ceramic capacitor placed within 2 mm of pin to suppress switching noise. |
Key Features
| Feature | Design Value |
|---|---|
| Asynchronous Set/Reset | Independent high-level assertion overrides clock and data - enables deterministic state initialization in safety-critical power sequencing. |
| Wide Supply Range | 3–18 V operation - eliminates need for separate voltage regulators when interfacing with diverse subsystems (e.g., 3.3 V MCU + 12 V sensor bus). |
| Symmetrical Output Drive | Matched sourcing/sinking capability (±6.8 mA @ VDD = 15 V) - ensures consistent rise/fall times and reduces duty-cycle distortion in clock dividers. |
| Low Input Current | ≤0.1 µA at 18 V and 25°C - permits direct connection to high-impedance sources (e.g., RC timers, potentiometers) without loading errors. |
| Industrial Temp Range | –55°C to +125°C operation - validated for deployment in uncontrolled environments like solar inverters, railway signaling, and oil-field controllers. |
Applications
| Power Button Debouncing | Divide-by-Two Clock Generator |
|---|---|
|
Use Scenario: Eliminates mechanical switch bounce in front-panel power controls for medical devices and industrial HMIs. IC Role / Device Role / Timing Role: Dual flip-flop configured as synchronized SR latch - samples switch state on first clock edge, holds stable output until next press. Use Value: Replaces RC+Schmitt trigger networks with deterministic, temperature-stable edge detection requiring no recalibration over life. |
Use Scenario: Generates precise 50% duty-cycle clocks from master oscillators in PLC timing modules and test equipment. IC Role / Device Role / Timing Role: Single-section wired as toggle (Q̅ → D) - divides input frequency by two with zero jitter accumulation per stage. Use Value: Delivers sub-nanosecond edge alignment between Q and Q̅ outputs, enabling clean clock distribution without external delay matching. |
| Shift Register Stage | State Memory Latch |
|
Use Scenario: Serial-to-parallel conversion in LED matrix drivers for building automation displays and signage. IC Role / Device Role / Timing Role: Cascaded D-flip-flops - shifts data bit-by-bit on each clock pulse, with parallel Q outputs driving column drivers. Use Value: Supports 10+ stage chains with guaranteed 45 ns propagation margin at 15 V, eliminating race conditions in multi-digit displays. |
Use Scenario: Retaining configuration bits (e.g., calibration flags, mode selection) during microcontroller sleep cycles in portable diagnostics gear. IC Role / Device Role / Timing Role: Standalone non-volatile memory element - holds state indefinitely with <1 µA quiescent draw at 5 V. Use Value: Extends battery life beyond 10 years in always-on monitoring nodes without EEPROM wear-out or refresh overhead. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual D-type flip-flop applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| CD4013BE | Same die, PDIP-14 package (19.3 × 6.35 mm); higher thermal resistance (RθJA = 47.1°C/W vs. 92.5°C/W for SOIC). | Better suited for prototyping or through-hole assembly; not recommended for high-density SMT layouts. | Select CD4013BE only when hand-soldering or breadboarding is required; CD4013BME4 preferred for automated production. |
| SN74HC74DR | CMOS HC-family; narrower 2–6 V supply range; faster 25 ns max tPD but lower noise margin (0.5 V @ VCC = 5 V). | Optimized for 3.3 V/5 V systems with tight timing budgets; unsuitable for 12 V industrial rails or wide-temp operation. | Choose SN74HC74DR for speed-critical 5 V logic; retain CD4013BME4 when supply flexibility, noise immunity, or extended temperature range is mandatory. |
Compared with CD4013BE and SN74HC74DR, the CD4013BME4 uniquely balances wide-voltage operation (3–18 V), industrial temperature tolerance (–55°C to +125°C), and proven reliability in safety-rated power infrastructure - making it the default choice where interoperability across legacy and modern rails is non-negotiable.
Availability
CD4013BME4 is available at Aetrix Electronics and suitable for power delivery sequencing, grid infrastructure monitoring, and medical device control requiring stable component supply across extended temperature and voltage ranges.
Supply support for CD4013BME4 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and high-reliability logic solutions for industrial, automotive, and aerospace markets.
The CD4013BME4 belongs to TI's legacy CMOS logic family designed for robust, low-power digital control in harsh environments - emphasizing wide supply tolerance, ESD resilience, and long-term parametric stability.
FAQ
What is the maximum clock frequency supported by the CD4013BME4 at 5 V supply?
The CD4013BME4 supports a maximum clock input frequency of 7 MHz (typical) at VDD = 5 V, with minimum pulse width of 70 ns. This is validated under standard test conditions (TA = 25°C, CL = 50 pF, RL = 20 kΩ) and accounts for propagation delay and setup/hold timing margins. Operation above this frequency risks metastability or incorrect state capture in the CD4013BME4 flip-flop sections.
Does the CD4013BME4 support asynchronous reset functionality?
Yes, the CD4013BME4 provides fully asynchronous active-high RESET inputs (pins 4 and 10) that force Q = 0 and Q̅ = 1 immediately, independent of clock or data signals. This function operates across the full supply range (3–18 V) and temperature range (–55°C to +125°C), making it suitable for fail-safe power-up initialization in the CD4013BME4-based designs.
Can the CD4013BME4 operate reliably at 3.3 V supply voltage?
Yes, the CD4013BME4 is fully specified down to 3 V supply voltage, with guaranteed performance including VIHmin = 2.1 V and VILmax = 0.9 V at VDD = 3.3 V (interpolated from datasheet curves). Input thresholds scale linearly with VDD, ensuring compatibility with 3.3 V microcontrollers and logic families when using the CD4013BME4 in mixed-voltage systems.
What is the thermal resistance (RθJA) of the CD4013BME4 in its SOIC-14 package?
The CD4013BME4 in SOIC-14 (D) package has a junction-to-ambient thermal resistance (RθJA) of 92.5°C/W, measured under JEDEC JESD51-2 conditions. This value assumes a standard 2-layer PCB with 1 in² copper pour; actual thermal performance improves with additional copper area or thermal vias. The CD4013BME4 remains within safe operating limits up to 125°C ambient when dissipating ≤5.4 mW per channel.
How does the CD4013BME4 handle floating inputs, and what is the recommended practice?
The CD4013BME4 CMOS inputs must never be left floating due to undefined logic states and potential shoot-through current. Per TI's layout guidelines, all unused inputs (e.g., unused SET/RESET pins) must be tied to VDD or VSS via low-impedance connections - typically 10 kΩ pull-up/down resistors. This prevents oscillation and ensures deterministic behavior in the CD4013BME4, especially under temperature extremes or EMI exposure.
CD4013BME4 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- 4000B
- Package/Case:
- 14-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tube
- Product Status:
- Discontinued at Digi-Key
- Function:
- Set(Preset) and Reset
- Type:
- D-Type
- Output Type:
- Complementary
- Number of Elements:
- 2
- Number of Bits per Element:
- 1
- Clock Frequency:
- 24 MHz
- Max Propagation Delay @ V, Max CL:
- 90ns @ 15V, 50pF
- Trigger Type:
- Positive Edge
- Current - Output High, Low:
- 6.8mA, 6.8mA
- Voltage - Supply:
- 3V ~ 18V
- Current - Quiescent (Iq):
- 4 µA
- Input Capacitance:
- 5 pF
- Operating Temperature:
- -55°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 14-SOIC
CD4013BME4 FAQ
1.How can I place an order for CD4013BME4 through Aetrix?
Please submit a Request for Quotation (RFQ) for CD4013BME4 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for CD4013BME4 reliable?
The price and inventory of CD4013BME4 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for CD4013BME4 is usually 5 days.
3.What payment methods are accepted for CD4013BME4?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for CD4013BME4 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for CD4013BME4?
CD4013BME4 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your CD4013BME4 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for CD4013BME4?
For technical support, including CD4013BME4 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your CD4013BME4 requirements.
6.How does Aetrix verify that CD4013BME4 is sourced from the original manufacturer or authorized distributors?
All CD4013BME4 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that CD4013BME4 meets industry standards.
7.What is the process for return or replacement of CD4013BME4?
All CD4013BME4 units undergo pre-shipment inspection (PSI). If there is an issue with CD4013BME4, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The CD4013BME4 part is unused and in its original packaging.
Return procedure for CD4013BME4:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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