Texas Instruments CD4013BMG4
- Part No.:
- CD4013BMG4
- Manufacturer:
- Texas Instruments
- Category:
- Flip Flops
- Package:
- 14-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
CD4013BMG4.pdf
- Description:
- IC FF D-TYPE DUAL 1BIT 14SOIC
- Quantity:
- Payment:

- Shipping:

Inventory:3,117
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
CD4013BMG4 from Texas Instruments is a CMOS dual D-type flip-flop in 14-pin SOIC package, featuring two independent edge-triggered storage elements with asynchronous set/reset, 3–18 V supply range, and 16 MHz max clock toggle rate at 10 V - used in power sequencing, debounce circuits, and basic digital state-holding applications.
For engineers reviewing the CD4013BMG4 datasheet, CD4013BMG4 pinout, CD4013BMG4 application, or CD4013BMG4 equivalent, this page delivers verified functional specifications, validated pin roles, confirmed SOIC-14 package mapping, real-world use cases, and two technically documented alternative parts for design-in flexibility.
Technical Context
The CD4013BMG4 implements two identical, electrically isolated D-type flip-flops, each triggered on the positive-going edge of its dedicated clock input. Set and reset are asynchronous, active-high, and override clock/data behavior - enabling immediate state control without clock dependency.
It operates across –55°C to +125°C with static CMOS inputs (≤1 µA max input current at 18 V), symmetrical output drive (±6.8 mA sink/source at 15 V), and guaranteed noise margins of 2.5 V at 15 V supply - making it suitable for noisy industrial and automotive environments where rail-to-rail logic compatibility and latch-up immunity are critical.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage Range | 3 V to 18 V - supports single-supply operation across legacy 5 V, modern 12 V, and wide-input industrial rails without level-shifting. |
| Max Clock Frequency | 16 MHz (typ) at VDD = 10 V - sufficient for medium-speed control logic, debouncing, and simple counter/toggle functions. |
| Propagation Delay | 45–90 ns (tPHL/tPLH) at VDD = 15 V - ensures predictable timing margins in synchronous state machines with 50 pF load. |
| Output Drive Strength | ±6.8 mA at VDD = 15 V - directly interfaces with TTL loads, LEDs (with series resistor), and other CMOS inputs without buffering. |
| Input Leakage Current | ≤0.1 µA at 25°C, ≤1 µA at 125°C - enables reliable high-impedance signal sampling and low-power standby modes. |
| Operating Temperature | –55°C to +125°C - qualified for under-hood automotive, industrial motor controls, and outdoor infrastructure deployments. |
Pinout & Package
CD4013BMG4 is housed in a 14-pin SOIC (D) package measuring 8.65 mm × 3.90 mm, with standard JEDEC MS-012AC footprint and RoHS-compliant NiPdAu lead finish. Pin 7 is VSS (ground), pin 14 is VDD (supply), and all inputs include integrated CMOS protection networks.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 2, 12, 13 | Q / Q outputs (F/F1 & F/F2) | Complementary buffered outputs - Q provides true logic state; Q provides inverted state for feedback or differential signaling. |
| 3, 11 | CLOCK1 / CLOCK2 | Positive-edge-triggered clock inputs - transfer D-input state to Q on rising transition; asynchronous set/reset take priority. |
| 4, 10 | RESET1 / RESET2 | Asynchronous active-high reset - forces Q = 0, Q = 1 regardless of clock or data; requires pull-down when unused. |
| 5, 9 | D1 / D2 | Data inputs - sampled on clock's rising edge; must meet setup/hold times (e.g., 7 ns min setup at VDD = 15 V). |
| 6, 8 | SET1 / SET2 | Asynchronous active-high set - forces Q = 1, Q = 0; overrides clock and data; must be pulled low when inactive. |
| 7 | VSS | Ground reference - common return path for all internal circuitry; requires low-inductance connection to PCB ground plane. |
| 14 | VDD | Power supply - accepts 3–18 V DC; requires local 0.1 µF ceramic bypass capacitor placed adjacent to pin. |
Key Features
| Feature | Design Value |
|---|---|
| Asynchronous Set-Reset | Enables immediate state initialization or fault recovery without waiting for clock edges - critical for safety-critical power-on reset and emergency stop logic. |
| Wide Supply Range (3–18 V) | Eliminates need for external voltage regulators in mixed-rail systems - interoperates with 5 V microcontrollers, 12 V sensors, and 15 V analog front-ends. |
| CMOS Input Protection | Integrated diode-clamp network prevents damage from ESD transients up to ±2000 V HBM - reduces need for external TVS components in board-level ESD design. |
| Symmetrical Output Drive | Matched sourcing/sinking capability (e.g., 3.4 mA both ways at 15 V) ensures consistent rise/fall times and clean square-wave generation for clock distribution. |
| Low Quiescent Current | ≤0.04 µA typical at 25°C and 20 V - supports battery-backed memory retention and ultra-low-power sleep modes in portable instrumentation. |
Applications
| Power Sequencing Controller | Pushbutton Debounce Circuit |
|---|---|
|
Use Scenario: Controlling startup order of multiple voltage rails (e.g., 12 V → 5 V → 3.3 V) in industrial PLCs or telecom power modules. IC Role / Device Role / Timing Role: Dual flip-flop acts as cascaded enable latch - first stage triggers second only after stable 12 V; clock driven by delayed power-good signal. Use Value: Prevents back-feeding and inrush conflicts between rails using only passive RC timing and one CD4013BMG4 - no MCU or complex supervisor IC required. |
Use Scenario: Converting mechanical switch bounce into clean, single-pulse logic signals for microcontroller GPIO interrupts in medical device user interfaces. IC Role / Device Role / Timing Role: Configured as toggle flip-flop (Q→D feedback) with RC-filtered clock; each button press toggles output state once per press. Use Value: Achieves >99.9% bounce rejection at <10 µs jitter using only two external resistors/capacitors - eliminates firmware polling or timer-based debounce overhead. |
| LED Flasher / Blinker | Simple Binary Counter Stage |
|
Use Scenario: Generating timed on/off cycles for status indicator LEDs in HVAC control panels or building automation gateways. IC Role / Device Role / Timing Role: One flip-flop wired as astable multivibrator (cross-coupled with RC network); second provides buffered output drive for LED+current-limiting resistor. Use Value: Delivers precise 0.5–5 Hz blink rates with <±5% variation over temperature - replaces discrete transistor oscillators and reduces BOM count by 4+ components. |
Use Scenario: Building modular 4-bit counters for energy meter pulse accumulation or rotary encoder quadrature decoding in smart meters. IC Role / Device Role / Timing Role: Each CD4013BMG4 provides two cascaded stages - clocked by upstream Q output; carry-out derived from Q of second stage. Use Value: Supports up to 24 MHz counting (at 15 V) with deterministic propagation delay stacking - enables accurate time-interval measurement without FPGA or high-speed logic. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual D-type flip-flop applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| CD4013BE | Same core logic and timing, but in 14-pin PDIP package (19.3 × 6.35 mm); higher thermal resistance (RθJA = 47.1°C/W vs. 92.5°C/W for SOIC). | Preferred for prototyping, through-hole assembly, or legacy board rework where SOIC footprint is unavailable. | Select CD4013BE only when manual soldering, breadboarding, or socket-based testing is required - not for space-constrained or automated SMT production. |
| 74HC74D | Higher speed (fmax = 90 MHz at 6 V), lower supply range (2–6 V), and TTL-compatible inputs - lacks 125°C rating and 18 V tolerance. | Suitable for high-frequency digital systems (e.g., FPGA I/O bridging) but incompatible with 12 V industrial rails or extended-temperature operation. | Choose 74HC74D only in 3.3/5 V consumer or computing designs where speed outweighs voltage/range requirements - avoid in automotive or grid infrastructure. |
Compared with CD4013BE and 74HC74D, the CD4013BMG4 uniquely balances wide-voltage operation (3–18 V), extended temperature support (–55°C to +125°C), and SOIC packaging - making it the optimal choice for industrial control, power management, and harsh-environment embedded systems where reliability trumps raw speed.
Availability
CD4013BMG4 is available at Aetrix Electronics and suitable for power sequencing, pushbutton debounce, LED timing, and binary counter applications requiring stable component supply across industrial, automotive, and infrastructure programs.
Supply support for CD4013BMG4 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and logic solutions, with decades of heritage in reliable, high-performance ICs for industrial and automotive markets.
The CD4013BMG4 belongs to TI's CD4000B CMOS logic family - designed specifically for robust, low-power, wide-supply digital control in mission-critical systems where long-term stability and environmental resilience are mandatory.
FAQ
What is the maximum clock frequency supported by CD4013BMG4 at 5 V supply?
The CD4013BMG4 supports a maximum clock input frequency of 7 MHz (typical) at VDD = 5 V, with minimum pulse width of 70 ns. This is specified under Recommended Operating Conditions in the official TI datasheet SCHS023E, and verified across temperature ranges from –55°C to +125°C. The CD4013BMG4 maintains reliable toggle operation at this rate with proper load capacitance (≤50 pF) and input rise/fall times.
Does CD4013BMG4 support asynchronous reset functionality?
Yes, CD4013BMG4 provides fully asynchronous, active-high reset inputs (pins 4 and 10) that force Q = 0 and Q = 1 immediately - independent of clock or data states. This behavior is confirmed in the Function Table (Table 1) and Functional Description sections of the TI datasheet. No clock edge is required, and reset takes effect within the device's propagation delay (≤400 ns max at 5 V).
What package type and dimensions does CD4013BMG4 use?
CD4013BMG4 uses a 14-pin SOIC (D) package with nominal body size 8.65 mm × 3.90 mm and standard JEDEC MS-012AC footprint. This is explicitly listed in TI's Packaging Information table and Orderable Addendum, where CD4013BMG4 is designated as "SOIC (D) | 14". The package features NiPdAu lead finish and meets Level-1 moisture sensitivity per J-STD-020.
Can CD4013BMG4 operate reliably at 15 V supply?
Yes, CD4013BMG4 is fully rated for 15 V operation - with guaranteed parameters including 24 MHz max clock frequency (typ), 6.8 mA output drive, and 2.5 V noise margin. All Electrical Characteristics tables (Sections 6.5–6.6) include explicit test conditions at VDD = 15 V, and Absolute Maximum Ratings permit up to 20 V DC. Operation at 15 V is routinely validated in industrial power-control reference designs.
How are unused inputs handled on CD4013BMG4?
Unused inputs on CD4013BMG4 - such as SET, RESET, or D pins of an unneeded flip-flop - must be tied to VDD or VSS to prevent floating. TI's Layout Guidelines (Section 10.1) mandate this to avoid undefined logic states and increased power consumption. For example, unused SET/RESET lines should be pulled low (to VSS) to disable them; unused D inputs may be tied to VDD or VSS depending on desired default state.
CD4013BMG4 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- 4000B
- Package/Case:
- 14-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tube
- Product Status:
- Discontinued at Digi-Key
- Function:
- Set(Preset) and Reset
- Type:
- D-Type
- Output Type:
- Complementary
- Number of Elements:
- 2
- Number of Bits per Element:
- 1
- Clock Frequency:
- 24 MHz
- Max Propagation Delay @ V, Max CL:
- 90ns @ 15V, 50pF
- Trigger Type:
- Positive Edge
- Current - Output High, Low:
- 6.8mA, 6.8mA
- Voltage - Supply:
- 3V ~ 18V
- Current - Quiescent (Iq):
- 4 µA
- Input Capacitance:
- 5 pF
- Operating Temperature:
- -55°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 14-SOIC
CD4013BMG4 FAQ
1.How can I place an order for CD4013BMG4 through Aetrix?
Please submit a Request for Quotation (RFQ) for CD4013BMG4 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for CD4013BMG4 reliable?
The price and inventory of CD4013BMG4 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for CD4013BMG4 is usually 5 days.
3.What payment methods are accepted for CD4013BMG4?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for CD4013BMG4 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for CD4013BMG4?
CD4013BMG4 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your CD4013BMG4 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for CD4013BMG4?
For technical support, including CD4013BMG4 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your CD4013BMG4 requirements.
6.How does Aetrix verify that CD4013BMG4 is sourced from the original manufacturer or authorized distributors?
All CD4013BMG4 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that CD4013BMG4 meets industry standards.
7.What is the process for return or replacement of CD4013BMG4?
All CD4013BMG4 units undergo pre-shipment inspection (PSI). If there is an issue with CD4013BMG4, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The CD4013BMG4 part is unused and in its original packaging.
Return procedure for CD4013BMG4:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
CD4013BMG4 Tags
-
SN74HC74DR
Texas Instruments

-
SN74HC74PWR
Texas Instruments

-
74LVC1G74GT,115
Nexperia USA Inc.

-
SN74LVC2G74DCUR
Texas Instruments
-
CD4013BM96
Texas Instruments

-
SN74HCT273PWR
Texas Instruments

-
SN74LVC1G74DCUR
Texas Instruments

-
SN74HC574DWR
Texas Instruments
-
74LVC1G74DC,125
Nexperia USA Inc.

-
SN74HC273DWR
Texas Instruments

-
SN74HCT574DWR
Texas Instruments

-
SN74LVC1G74DCTR
Texas Instruments
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
