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Texas Instruments CD4013BMT
- Part No.:
- CD4013BMT
- Manufacturer:
- Texas Instruments
- Category:
- Flip Flops
- Package:
- 14-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
CD4013BMT.pdf
- Description:
- IC FF D-TYPE DUAL 1BIT 14SOIC
- Quantity:
- Payment:
- Shipping:
Inventory:2,366
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Product details
Overview
CD4013BMT from Texas Instruments is a CMOS dual D-type flip-flop IC comprising two independent, edge-triggered storage elements. Each section features asynchronous set/reset, data, clock, Q and Q̅ outputs, operates from 3 V to 18 V supply, delivers 16 MHz max clock toggle rate at 10 V, and supports industrial temperature range (–55°C to +125°C). It is used in power button debouncing, divide-by-two frequency division, and shift register stages.
For engineers reviewing the CD4013BMT datasheet, CD4013BMT pinout, CD4013BMT application, or CD4013BMT equivalent, key selection criteria include its wide VDD range, asynchronous control capability, symmetrical output drive, low quiescent current (≤1 µA at 25°C), and SOIC-14 packaging with verified 14-pin functional mapping.
Technical Context
The CD4013BMT implements two identical, positive-edge-triggered D flip-flops with fully independent input sets (D, CLK, SET, RESET) and complementary outputs (Q, Q̅). Its static CMOS architecture enables rail-to-rail logic swing, high noise immunity (2.5 V at 15 V VDD), and ultra-low input leakage (≤10 nA at 25°C).
Each flip-flop operates asynchronously for SET/RESET-asserting high on either line forces immediate Q/Q̅ state change regardless of clock activity-while data transfer occurs only on the rising edge of CLK when both SET and RESET are low. Propagation delays are tightly matched (tPHL/tPLH ≤ 90 ns typical at 15 V, CL = 50 pF).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage Range | 3 V to 18 V - supports single-supply operation across battery, industrial, and legacy logic rails without level shifting. |
| Max Clock Frequency | 16 MHz (typical at VDD = 10 V) - enables reliable use in medium-speed timing, counting, and synchronization up to ~62.5 ns minimum clock period. |
| Propagation Delay | 45–90 ns (tPHL/tPLH, VDD = 15 V, CL = 50 pF) - ensures predictable setup/hold timing margins in cascaded logic or feedback configurations. |
| Input Leakage Current | ≤10 nA at 25°C, VDD = 18 V - minimizes unintended node charging in high-impedance or battery-powered circuits. |
| Output Drive Strength | ±6.8 mA (IOH/IOL, VDD = 15 V) - sufficient to directly drive multiple 74HC inputs or small LEDs without external buffers. |
| Operating Temperature | –55°C to +125°C - qualified for automotive under-hood, military, and industrial control environments with full parameter guarantee. |
Pinout & Package
CD4013BMT is supplied in a 14-pin SOIC (Small Outline Integrated Circuit) package with 8.65 mm × 3.90 mm body size, gull-wing leads, and standard JEDEC MS-012AC footprint. Pin 1 is marked by notch or bevel; pin numbering follows counterclockwise convention from top-left corner.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | Q1 | Non-inverted output of Flip-Flop 1 - provides true logic state synchronized to CLK1 edge when SET1/RESET1 inactive. |
| 2 | Q1̅ | Inverted output of Flip-Flop 1 - complements Q1; used for toggle feedback or differential signaling. |
| 3 | CLOCK1 | Positive-edge clock input for FF1 - triggers D1→Q1 transfer only on rising transition; asynchronous controls override clock action. |
| 4 | RESET1 | Asynchronous reset for FF1 - high-level assertion forces Q1 = 0, Q1̅ = 1 immediately, independent of CLOCK1. |
| 5 | D1 | Data input for FF1 - sampled on CLOCK1 rising edge if RESET1 = RESET2 = 0 and SET1 = 0. |
| 6 | SET1 | Asynchronous set for FF1 - high-level assertion forces Q1 = 1, Q1̅ = 0 immediately, overriding clock and data. |
| 7 | VSS | Ground reference - must be connected to system common; all internal logic referenced to this node. |
| 8 | SET2 | Asynchronous set for FF2 - functionally identical to SET1 but isolated to second flip-flop. |
| 9 | D2 | Data input for FF2 - independent of D1; enables dual-channel storage in single package. |
| 10 | RESET2 | Asynchronous reset for FF2 - independent of RESET1; allows individual channel initialization. |
| 11 | CLOCK2 | Positive-edge clock input for FF2 - electrically isolated from CLOCK1; supports independent timing domains. |
| 12 | Q2̅ | Inverted output of Flip-Flop 2 - matches Q1̅ functionality for second channel. |
| 13 | Q2 | Non-inverted output of Flip-Flop 2 - primary output for second storage element. |
| 14 | VDD | Positive supply rail - powers both flip-flops; bypass capacitor (0.1 µF) required near pin for stable operation. |
Key Features
| Feature | Design Value |
|---|---|
| Asynchronous Set-Reset | Enables immediate state forcing without clock dependency - critical for power-on initialization, fault recovery, and emergency shutdown paths. |
| Wide Supply Range (3–18 V) | Eliminates need for voltage translation in mixed-supply systems - interoperable with 3.3 V microcontrollers, 5 V legacy peripherals, and 12 V industrial rails. |
| Symmetrical Output Characteristics | Matched rise/fall times and drive strength (±6.8 mA) ensure clean square-wave generation and reduce timing skew in clock division. |
| Low Input Current (≤10 nA) | Permits direct connection to high-impedance sources (e.g., RC timers, sensor outputs) without loading errors or signal degradation. |
| Industrial Temperature Rating | Guaranteed operation from –55°C to +125°C - validated for deployment in uncontrolled ambient environments including motor drives and outdoor infrastructure. |
Applications
| Power Button Debouncing | Frequency Division (÷2) |
|---|---|
Use Scenario: Mechanical push-button switch interfaced to a microcontroller GPIO, where contact bounce causes multiple unintended interrupts. IC Role / Device Role / Timing Role: CD4013BMT acts as a synchronous edge-triggered latch, using one flip-flop configured as a toggle with clock tied to button signal and debounced output fed to MCU interrupt pin. Use Value: Eliminates software debounce overhead and guarantees single, clean edge per press - reduces firmware complexity and improves real-time response. | Use Scenario: Generating a precise 50% duty-cycle clock signal at half the frequency of an input oscillator (e.g., converting 1 MHz to 500 kHz). IC Role / Device Role / Timing Role: CD4013BMT functions as a divide-by-two counter: Q output is fed back to D input, and CLK receives master clock; Q toggles on each rising edge. Use Value: Provides hardware-based, jitter-free division with no propagation delay accumulation - superior to cascaded logic gates in timing-critical applications. |
| Shift Register Stage | Memory Hold / Data Latching |
Use Scenario: Serial-to-parallel conversion in LED matrix drivers or sensor data acquisition where multiple bits arrive sequentially over a single line. IC Role / Device Role / Timing Role: Two CD4013BMT flip-flops serve as adjacent stages in a 2-bit shift register, clocked synchronously to advance data from D1→Q1→D2→Q2. Use Value: Enables compact, low-power serial interface expansion without dedicated shift-register ICs - reduces BOM count and PCB area. | Use Scenario: Capturing and holding analog-to-digital converter (ADC) output values until read by host processor, preventing data loss during bus arbitration. IC Role / Device Role / Timing Role: CD4013BMT stores digital word from ADC parallel bus using one flip-flop per bit; clock aligned to EOC (end-of-conversion) signal. Use Value: Provides glitch-free, metastability-resistant storage with guaranteed setup/hold timing - avoids race conditions in mixed-signal subsystems. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual D-type flip-flop applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| CD4013BE | PDIP-14 package; higher thermal resistance (RθJA = 47.1°C/W); same electrical specs and pinout. | Preferred for prototyping, through-hole assembly, or legacy board designs requiring socket compatibility. | Select CD4013BE when manual soldering, breadboarding, or mechanical robustness outweighs space constraints. |
| SN74HC74DR | Higher speed (fmax = 78 MHz at 6 V); narrower VCC range (2–6 V); TTL-compatible inputs; different pinout (no dedicated SET/RESET per FF). | Better suited for high-frequency digital systems (e.g., FPGA I/O bridging) but lacks independent asynchronous controls. | Choose SN74HC74DR only if operating below 6 V and requiring faster toggle rates; verify clock-domain isolation requirements. |
Compared with CD4013BE and SN74HC74DR, the CD4013BMT offers unique value in wide-voltage industrial applications requiring independent asynchronous set/reset per flip-flop in surface-mount form - neither alternative replicates this exact combination of voltage range, control flexibility, and SOIC packaging.
Availability
CD4013BMT is available at Aetrix Electronics and suitable for power delivery, grid infrastructure, and medical device applications requiring stable component supply across extended temperature ranges and long product lifecycles.
Supply support for CD4013BMT includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and logic solutions, with decades of expertise in CMOS technology and industrial-grade reliability.
The CD4013BMT belongs to TI's CD4000B series of buffered CMOS logic devices, designed specifically for robust operation in harsh environments where wide supply tolerance, low power, and high noise immunity are essential.
FAQ
What is the maximum clock frequency supported by the CD4013BMT?
The CD4013BMT supports a maximum clock input frequency of 16 MHz typical at VDD = 10 V, and up to 24 MHz at VDD = 15 V. These values assume CL = 50 pF and TA = 25°C; actual usable frequency decreases with higher temperature, larger capacitive loads, or lower supply voltage. The CD4013BMT datasheet specifies fCL min/max across the full operating range, and design margin should account for worst-case propagation delay (90 ns at 15 V).
Does the CD4013BMT support asynchronous set and reset on both flip-flops?
Yes, the CD4013BMT provides fully independent asynchronous SET and RESET inputs for each of its two D-type flip-flops (SET1/RESET1 for FF1; SET2/RESET2 for FF2). A high-level assertion on either SET or RESET forces immediate, clock-independent state change - Q = 1 or Q = 0 respectively - making the CD4013BMT suitable for fail-safe control and initialization sequences.
What package type is used for the CD4013BMT?
The CD4013BMT uses a 14-pin SOIC (Small Outline Integrated Circuit) package with body dimensions of 8.65 mm × 3.90 mm. This surface-mount package is RoHS-compliant, features NIPDAU lead finish, and carries a moisture sensitivity level (MSL) rating of Level-1 (unlimited floor life at ≤30°C/60% RH), per TI's orderable addendum.
Can the CD4013BMT operate from a 3.3 V supply?
Yes, the CD4013BMT is fully specified to operate from 3 V to 18 V, including 3.3 V nominal supplies. At VDD = 3.3 V, it delivers guaranteed logic thresholds (VIH ≥ 2.0 V, VIL ≤ 1.3 V), output drive (±1.5 mA), and timing (fCL ≥ 3.5 MHz), though propagation delay increases versus higher voltages. System designers must verify noise margin and fanout requirements at 3.3 V per the CD4013BMT electrical characteristics table.
Is the CD4013BMT pin-compatible with other CD4013 variants like CD4013BM or CD4013BE?
Yes, all CD4013B variants - including CD4013BMT, CD4013BM, and CD4013BE - share identical 14-pin functional pinouts and electrical behavior. Differences are strictly in packaging (SOIC vs PDIP vs CDIP) and thermal/mounting characteristics; no circuit redesign or layout change is needed when substituting within the same package family. The CD4013BMT pin mapping matches the standard CD4013B logic diagram and function table exactly.
CD4013BMT Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- 4000B
- Package/Case:
- 14-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Function:
- Set(Preset) and Reset
- Type:
- D-Type
- Output Type:
- Complementary
- Number of Elements:
- 2
- Number of Bits per Element:
- 1
- Clock Frequency:
- 24 MHz
- Max Propagation Delay @ V, Max CL:
- 90ns @ 15V, 50pF
- Trigger Type:
- Positive Edge
- Current - Output High, Low:
- 6.8mA, 6.8mA
- Voltage - Supply:
- 3V ~ 18V
- Current - Quiescent (Iq):
- 4 µA
- Input Capacitance:
- 5 pF
- Operating Temperature:
- -55°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 14-SOIC
CD4013BMT FAQ
1.How can I place an order for CD4013BMT through Aetrix?
Please submit a Request for Quotation (RFQ) for CD4013BMT on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for CD4013BMT reliable?
The price and inventory of CD4013BMT are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for CD4013BMT is usually 5 days.
3.What payment methods are accepted for CD4013BMT?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for CD4013BMT transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for CD4013BMT?
CD4013BMT orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your CD4013BMT order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for CD4013BMT?
For technical support, including CD4013BMT datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your CD4013BMT requirements.
6.How does Aetrix verify that CD4013BMT is sourced from the original manufacturer or authorized distributors?
All CD4013BMT products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that CD4013BMT meets industry standards.
7.What is the process for return or replacement of CD4013BMT?
All CD4013BMT units undergo pre-shipment inspection (PSI). If there is an issue with CD4013BMT, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The CD4013BMT part is unused and in its original packaging.
Return procedure for CD4013BMT:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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