Texas Instruments CD4013BPWRG4
- Part No.:
- CD4013BPWRG4
- Manufacturer:
- Texas Instruments
- Category:
- Flip Flops
- Package:
- 14-TSSOP (0.173", 4.40mm Width)
- Datasheet:
-
CD4013BPWRG4.pdf
- Description:
- IC FF D-TYPE DUAL 1BIT 14TSSOP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
CD4013BPWRG4 from Texas Instruments is a CMOS dual D-type flip-flop IC with independent clock, data, set, and reset inputs per channel, Q/Q̅ buffered outputs, 3–18 V supply range, ±1 µA max input current at 18 V, and 16 MHz typical toggle rate at 10 V - used in power button debouncing, toggle counters, and shift register stages in industrial control logic.
For engineers reviewing the CD4013BPWRG4 datasheet, CD4013BPWRG4 pinout, CD4013BPWRG4 application, or CD4013BPWRG4 equivalent, key selection factors include its positive-edge-triggered D-flip-flop architecture, asynchronous set/reset capability, wide voltage operation, symmetrical output drive, and TSSOP-14 packaging for space-constrained PCBs.
Technical Context
The CD4013BPWRG4 implements two identical, electrically isolated D-type flip-flops in a single monolithic CMOS die. Each section features fully asynchronous set and reset inputs that override clock and data, enabling immediate state forcing without clock dependency.
It operates as a master-slave edge-triggered device: data at the D input is latched on the positive-going transition of CLOCK, with propagation delays (tPHL/tPLH) as low as 45 ns (typ) at VDD = 15 V and CL = 50 pF, and supports static operation down to 0 Hz with no minimum clock requirement.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Logic Type | Dual positive-edge-triggered D-type flip-flop with independent asynchronous set/reset per channel |
| Supply Voltage Range | 3 V to 18 V - enables direct interface with legacy 5 V, 12 V, and battery-backed systems without level shifting |
| Max Clock Frequency | 16 MHz (typ) at VDD = 10 V - sufficient for medium-speed timing, debounce, and basic counter applications |
| Input Current (max) | ±1 µA at VDD = 18 V and TA = 25°C - ensures ultra-low standby power in always-on monitoring circuits |
| Output Drive | ±6.8 mA (min) at VDD = 15 V - capable of directly driving LEDs, small relays, or CMOS/TTL fan-out loads |
| Propagation Delay | 45–90 ns (max) at VDD = 15 V - defines maximum achievable toggle rate and setup/hold timing margins |
| Operating Temperature | –55°C to +125°C - qualified for automotive under-hood, industrial motor control, and aerospace environments |
Pinout & Package
TSSOP-14 (PW) package: 5.00 mm × 4.40 mm body, 0.65 mm lead pitch, thin profile suitable for high-density PCB layouts and automated SMT assembly.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | Q1 | Non-inverted output of Channel 1 - active-high logic state mirror of D1 at clock edge |
| 2 | Q1̅ | Inverted output of Channel 1 - complements Q1; used for feedback or differential signaling |
| 3 | CLOCK1 | Positive-edge-sensitive clock input for Channel 1 - triggers data transfer only on rising transition |
| 4 | RESET1 | Asynchronous active-high reset for Channel 1 - forces Q1 = 0, Q1̅ = 1 regardless of clock or D |
| 5 | D1 | Data input for Channel 1 - sampled on CLOCK1 rising edge and transferred to Q1 |
| 6 | SET1 | Asynchronous active-high set for Channel 1 - forces Q1 = 1, Q1̅ = 0 regardless of clock or D |
| 7 | VSS | Ground reference - must be connected to system common return with low-impedance path |
| 8 | SET2 | Asynchronous active-high set for Channel 2 - independent control of second flip-flop |
| 9 | D2 | Data input for Channel 2 - functionally identical to D1 but electrically isolated |
| 10 | RESET2 | Asynchronous active-high reset for Channel 2 - independent of Channel 1 operation |
| 11 | CLOCK2 | Positive-edge-sensitive clock input for Channel 2 - may be tied to CLOCK1 or driven separately |
| 12 | Q2̅ | Inverted output of Channel 2 - complements Q2; supports toggle or complemented logic paths |
| 13 | Q2 | Non-inverted output of Channel 2 - primary output for second independent storage element |
| 14 | VDD | Positive supply rail - accepts 3–18 V DC; requires local 0.1 µF bypass capacitor per TI layout guidance |
Key Features
| Feature | Design Value |
|---|---|
| Asynchronous Set-Reset | Independent SET/RESET pins per channel enable immediate state control without clock dependency - critical for emergency stop or initialization sequences |
| Wide Supply Range | 3 V to 18 V operation allows direct integration into mixed-voltage systems (e.g., 3.3 V MCU control with 12 V actuator interface) |
| CMOS Input Protection | All inputs include integrated protection networks - withstands ±2000 V HBM ESD and reduces need for external TVS diodes |
| Symmetrical Output Drive | Matched sourcing/sinking capability (±6.8 mA min at 15 V) ensures consistent rise/fall times and noise immunity in bidirectional bus interfaces |
| Static Operation | No minimum clock frequency required - supports zero-Hz hold functions and ultra-low-power sleep-state retention |
Applications
| Power Button Debounce | Toggle Counter Stage |
|---|---|
|
Use Scenario: Eliminates mechanical switch bounce in front-panel power controls for industrial HMIs and medical devices. IC Role / Device Role / Timing Role: Dual flip-flop configured as synchronized SR latch - one section samples switch state, the other provides clean, glitch-free output. Use Value: Achieves reliable on/off detection without microcontroller firmware overhead or RC timing drift over temperature. |
Use Scenario: Forms divide-by-2 stage in binary counters for motor speed control or LED flash sequencing. IC Role / Device Role / Timing Role: Single flip-flop wired with Q̅ → D feedback - toggles Q output on every clock edge. Use Value: Provides precise 50% duty-cycle square wave with no external components, supporting stable timing up to 16 MHz. |
| Shift Register Element | State Latch for Sensor Interface |
|
Use Scenario: Implements serial-to-parallel conversion in low-pin-count sensor arrays (e.g., multi-channel temperature monitors). IC Role / Device Role / Timing Role: Cascaded CD4013BPWRG4 units - Q2 drives D1 of next stage; shared clock synchronizes data shift. Use Value: Reduces MCU GPIO usage by 50% versus parallel sensing, while maintaining deterministic timing via edge-triggered capture. |
Use Scenario: Captures and holds analog-to-digital converter (ADC) results during multiplexed acquisition in PLC I/O modules. IC Role / Device Role / Timing Role: One flip-flop stores conversion-ready flag; second holds digital result until read by host processor. Use Value: Prevents data loss during bus arbitration delays and enables synchronous read-back independent of ADC conversion timing. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual D-type flip-flop applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| CD4013BMG4 | SOIC-14 package (8.65 mm × 3.90 mm); higher thermal resistance (RθJA = 92.5°C/W vs. 121°C/W for TSSOP) | Better suited for through-hole prototyping or boards with legacy SOIC footprints; less dense than TSSOP | Select when board reworkability or hand-soldering is prioritized over miniaturization |
| SN74HC74DR | Higher speed (fmax = 60 MHz at 6 V); narrower supply (2–6 V); TTL-compatible inputs; no 12–18 V support | Optimized for 3.3 V/5 V digital systems only; unsuitable for 12 V industrial or battery-powered designs | Choose for high-speed, low-voltage logic where extended voltage range is unnecessary |
Compared with CD4013BMG4 and SN74HC74DR, the CD4013BPWRG4 uniquely balances ultra-wide supply range (3–18 V), industrial temperature tolerance (–55°C to +125°C), and compact TSSOP packaging - making it the only option among the three viable for 12 V automotive body electronics or 15 V analog front-end latching.
Availability
CD4013BPWRG4 is available at Aetrix Electronics and suitable for industrial control panels, medical device power management, and telecom infrastructure timing requiring stable component supply across extended temperature and voltage ranges.
Supply support for CD4013BPWRG4 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and logic ICs, with decades of heritage in CMOS logic design and industrial-grade reliability validation.
The CD4013B product line was engineered for robust, wide-voltage digital control in harsh environments - targeting applications where long-term stability, radiation tolerance, and supply flexibility outweigh raw speed requirements.
FAQ
What is the maximum clock frequency supported by the CD4013BPWRG4?
The CD4013BPWRG4 supports a maximum clock frequency of 16 MHz (typical) at VDD = 10 V and 24 MHz (typical) at VDD = 15 V, as specified in the Electrical Characteristics: Dynamic table. Actual usable frequency depends on load capacitance, supply voltage, and operating temperature - with derating required above 85°C ambient.
Does the CD4013BPWRG4 require external pull-up or pull-down resistors on unused inputs?
Yes - all unused inputs on the CD4013BPWRG4 must be tied to VDD or VSS to prevent floating states that cause excessive current draw and undefined logic behavior. This is explicitly required in TI's Layout Guidelines (Section 10.1) due to CMOS gate sensitivity, and applies to unused SET, RESET, D, and CLOCK pins.
Can the CD4013BPWRG4 operate from a 3.3 V supply?
Yes - the CD4013BPWRG4 is fully specified for operation from 3 V to 18 V, including 3.3 V nominal supplies. At 3.3 V, it delivers reduced output drive (±1.3 mA min) and lower maximum clock frequency (~3.5 MHz typ), but retains full functionality including asynchronous set/reset and static operation.
What is the meaning of the 'G4' suffix in CD4013BPWRG4?
The 'G4' suffix in CD4013BPWRG4 indicates RoHS-compliant packaging with NiPdAu (nickel-palladium-gold) lead finish and green molding compound, per Texas Instruments' standard ordering nomenclature. It confirms compliance with JEDEC J-STD-020 moisture sensitivity Level-1 and eliminates lead-based solder compatibility concerns.
How does the CD4013BPWRG4 handle simultaneous SET and RESET assertion?
When both SET and RESET are high simultaneously on the same channel of the CD4013BPWRG4, the outputs enter an indeterminate metastable state per the Function Table in Section 7.4. TI specifies this condition as invalid - designers must ensure mutually exclusive activation using external logic or timing constraints to guarantee predictable Q/Q̅ behavior.
CD4013BPWRG4 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- 4000B
- Package/Case:
- 14-TSSOP (0.173", 4.40mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Discontinued at Digi-Key
- Function:
- Set(Preset) and Reset
- Type:
- D-Type
- Output Type:
- Complementary
- Number of Elements:
- 2
- Number of Bits per Element:
- 1
- Clock Frequency:
- 24 MHz
- Max Propagation Delay @ V, Max CL:
- 90ns @ 15V, 50pF
- Trigger Type:
- Positive Edge
- Current - Output High, Low:
- 6.8mA, 6.8mA
- Voltage - Supply:
- 3V ~ 18V
- Current - Quiescent (Iq):
- 4 µA
- Input Capacitance:
- 5 pF
- Operating Temperature:
- -55°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 14-TSSOP
CD4013BPWRG4 FAQ
1.How can I place an order for CD4013BPWRG4 through Aetrix?
Please submit a Request for Quotation (RFQ) for CD4013BPWRG4 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for CD4013BPWRG4 reliable?
The price and inventory of CD4013BPWRG4 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for CD4013BPWRG4 is usually 5 days.
3.What payment methods are accepted for CD4013BPWRG4?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for CD4013BPWRG4 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for CD4013BPWRG4?
CD4013BPWRG4 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your CD4013BPWRG4 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for CD4013BPWRG4?
For technical support, including CD4013BPWRG4 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your CD4013BPWRG4 requirements.
6.How does Aetrix verify that CD4013BPWRG4 is sourced from the original manufacturer or authorized distributors?
All CD4013BPWRG4 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that CD4013BPWRG4 meets industry standards.
7.What is the process for return or replacement of CD4013BPWRG4?
All CD4013BPWRG4 units undergo pre-shipment inspection (PSI). If there is an issue with CD4013BPWRG4, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The CD4013BPWRG4 part is unused and in its original packaging.
Return procedure for CD4013BPWRG4:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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