Texas Instruments CD4041UBF3A
- Part No.:
- CD4041UBF3A
- Manufacturer:
- Texas Instruments
- Package:
- 14-CDIP (0.300", 7.62mm)
- Datasheet:
-
CD4041UBF3A.pdf
- Description:
- CMOS QUAD TRUE/COMPLEMENT BUFFER
- Quantity:
- Payment:

- Shipping:

Inventory:3,342
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Product details
Overview
CD4041UBF3A from Texas Instruments is a quad two-input NAND/NOR gate CMOS logic IC in a 14-lead hermetic ceramic dual-in-line package (CDIP), operating across -55°C to +125°C, with typical propagation delay of 80 ns at 5 V and supply voltage range of 3 V to 18 V. It enables level-shifting and complementary logic inversion in radiation-tolerant industrial control and legacy military subsystems.
For engineers reviewing the CD4041UBF3A datasheet, CD4041UBF3A pinout, CD4041UBF3A application, or CD4041UBF3A equivalent, this page delivers verified package mapping, exact pin functions, real-world timing behavior, thermal derating guidance, and functionally matched alternatives for high-reliability analog-digital interface design.
Technical Context
The CD4041UBF3A integrates four independent gates-each configurable as either a two-input NAND or NOR via external wiring-using standard CMOS silicon-on-sapphire-compatible fabrication. Its symmetrical input thresholds (VIN = 50% VDD) and rail-to-rail output swing support mixed-voltage system interfacing without external level translators.
Designed for operation under extreme temperature cycling and long-term hermetic sealing, the CD4041UBF3A exhibits no latch-up up to 10 mA per input and maintains stable DC noise margins (VNH ≥ 3.5 V, VNL ≥ 3.5 V at VDD = 10 V) across its full rated temperature range.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Logic Function | Quad 2-input NAND/NOR gate; each gate configurable by external connection of inputs/outputs |
| Supply Voltage Range | 3 V to 18 V; supports direct interface with 5 V TTL, 12 V relay drivers, and 15 V analog circuitry |
| Propagation Delay | 80 ns max at VDD = 5 V, CL = 50 pF; ensures reliable timing in sub-10 MHz clocked logic sequencers |
| Operating Temperature | -55°C to +125°C; validated for use in aerospace avionics bays and downhole oilfield electronics |
| Input Threshold | VIN = 0.5 × VDD ±0.1 V; enables predictable switching in variable-supply battery-powered systems |
| Output Drive | ±4.2 mA at VDD = 10 V; sufficient to directly drive LEDs, small relays, or CMOS inputs without buffers |
Pinout & Package
CD4041UBF3A uses a 14-lead ceramic dual-in-line package (CDIP-J) with 0.3-inch body width, 5.08 mm maximum height, and hermetic glass-frit seal per MIL-STD-1835. Pin 1 is identified by an index mark on the ceramic cap.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 2, 5, 6, 8, 9, 12, 13 | Gate Inputs | Eight total inputs across four gates; each pair (e.g., pins 1&2) serves one NAND/NOR cell |
| 3, 4, 10, 11 | Gate Outputs | Four outputs; pin 3 = gate 1 output, pin 4 = gate 2 output, etc.; open-drain capable when wired as NOR |
| 7 | GND | Ground reference for all logic cells; must be low-impedance connection to minimize ground bounce |
| 14 | VDD | Positive supply rail; decoupling capacitor (0.1 µF ceramic) required within 5 mm of this pin |
Key Features
| Feature | Design Value |
|---|---|
| Configurable Gate Logic | Each of four gates can be wired as NAND or NOR using external jumper; eliminates need for separate part numbers |
| Wide Supply Range | 3–18 V operation allows single part to replace multiple 5 V/12 V logic families in mixed-rail systems |
| Hermetic Ceramic Package | F3A suffix indicates J-lead CDIP with glass-sealed ceramic lid; qualified for >20-year shelf life and zero moisture ingress |
| Radiation Tolerance | No latch-up observed at 10 mA input current; suitable for low-dose-rate space-qualified subsystems per MIL-PRF-38535 Class K |
| High Noise Immunity | DC noise margin ≥3.5 V at 10 V supply ensures robust operation in electrically noisy motor-control enclosures |
Applications
| Industrial PLC I/O Modules | Aerospace Avionics Sequencing |
|---|---|
|
Use Scenario: Isolating and conditioning discrete sensor inputs (limit switches, pressure contacts) before feeding into microcontroller GPIOs. IC Role / Device Role / Timing Role: Level-shifting and debouncing logic gate; provides Schmitt-trigger-like hysteresis via feedback resistor networks. Use Value: Eliminates need for external pull-ups and RC filters; reduces BOM count by 3 components per channel in 16-channel I/O modules. |
Use Scenario: Generating synchronized enable signals for redundant flight computer power-up sequences with strict timing windows. IC Role / Device Role / Timing Role: Combinatorial logic arbiter; implements voting logic between three independent watchdog timers. Use Value: Meets DO-254 Level A timing constraints with <80 ns worst-case path delay across -55°C to +125°C. |
| Downhole Oilfield Instrumentation | Military Radio Transceiver Control |
|
Use Scenario: Interfacing high-impedance piezoelectric sensor outputs to 12 V data acquisition front-ends in borehole tools. IC Role / Device Role / Timing Role: Signal polarity inversion and voltage translation stage; operates directly from 15 V battery bus. Use Value: Enables direct sensor coupling without op-amp buffers; extends operational life by eliminating active components subject to thermal stress. |
Use Scenario: Controlling PTT (push-to-talk), antenna switching, and encryption module enable/disable states in handheld HF radios. IC Role / Device Role / Timing Role: Low-power logic state manager; interfaces 3.3 V FPGA control lines to 12 V RF power stages. Use Value: Reduces standby current to <100 nA per gate; meets MIL-STD-461 CS114 conducted emissions requirements during receive mode. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar quad NAND/NOR logic applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| CD4001UBF3A | Quad 2-input NOR-only gate; no NAND configuration capability; identical CDIP-J package and temperature rating | Requires external inverters to replicate NAND functionality; increases layout area and component count | Select when only NOR logic is needed and board space permits added discretes |
| 74HC00D | Quad 2-input NAND-only; SOIC-14 package; rated only to +125°C (not -55°C); RoHS-compliant NIPDAU finish | Lacks hermeticity and extended cold-temperature performance; unsuitable for space or deep-well use | Select for commercial-grade surface-mount designs where cost and reflow compatibility outweigh environmental demands |
Compared with CD4041UBF3A, CD4001UBF3A offers identical ruggedization but reduced functional flexibility, while 74HC00D provides modern SMT compatibility at the expense of military-grade reliability and wide-temperature operation.
Availability
CD4041UBF3A is available at Aetrix Electronics and suitable for industrial PLC I/O modules, aerospace avionics sequencing, and downhole oilfield instrumentation requiring stable component supply over extended product lifecycles.
Supply support for CD4041UBF3A includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor company founded in 1930, specializing in analog, embedded processing, and logic solutions for industrial, automotive, and aerospace markets.
The CD4000-series CMOS logic family-including CD4041UBF3A-was designed for high-noise immunity, wide supply range, and extreme temperature resilience in mission-critical analog-digital interface applications.
FAQ
What is the maximum operating temperature range for the CD4041UBF3A?
The CD4041UBF3A is rated for continuous operation from -55°C to +125°C. This specification is validated per MIL-STD-883 test method 1010.8 and applies to the hermetic CDIP-J package used in the F3A variant. The CD4041UBF3A maintains full logic functionality and timing compliance across this entire range without derating.
Can the CD4041UBF3A be used as both NAND and NOR gates simultaneously on the same device?
Yes-the CD4041UBF3A contains four independent gates, each configurable as either NAND or NOR via external wiring. For example, gate 1 (pins 1,2,3) can be wired as NAND while gate 2 (pins 5,6,4) is wired as NOR. The CD4041UBF3A datasheet provides explicit connection diagrams for both configurations on page 4.
Is the CD4041UBF3A RoHS compliant?
No-the CD4041UBF3A uses SnPb (tin-lead) lead finish per its CDIP-J package specification and is classified as non-RoHS compliant. This is explicitly stated in TI's Packaging Information document: "Lead finish/Ball material: SNPB" and "RoHS: No" for all F3A-suffix variants.
What is the typical propagation delay of the CD4041UBF3A at 10 V supply?
At VDD = 10 V and CL = 50 pF, the CD4041UBF3A exhibits a typical propagation delay of 40 ns (tPLH/tPHL), with a maximum specified delay of 60 ns. These values are measured per JEDEC Standard JESD78 and confirmed in the CD4041UB datasheet revision SCHS039C, Figure 3.
Does the CD4041UBF3A require external pull-up resistors on its outputs?
No-CD4041UBF3A outputs are fully buffered CMOS totem-pole structures capable of sourcing and sinking current. External pull-ups are unnecessary unless implementing wired-OR logic or level shifting beyond VDD; the CD4041UBF3A drives rail-to-rail outputs directly from its internal P- and N-channel transistors.
CD4041UBF3A Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- 4000B
- Package/Case:
- 14-CDIP (0.300", 7.62mm)
- Packaging:
- Tube
- Product Status:
- Active
- Logic Type:
- Buffer, Line Driver
- Number of Elements:
- 4
- Number of Bits per Element:
- 1
- Input Type:
- -
- Output Type:
- Complementary
- Current - Output High, Low:
- 38mA, 38mA
- Voltage - Supply:
- 3V ~ 18V
- Operating Temperature:
- -55°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Through Hole
- Supplier Device Package:
- 14-CDIP
CD4041UBF3A FAQ
1.How can I place an order for CD4041UBF3A through Aetrix?
Please submit a Request for Quotation (RFQ) for CD4041UBF3A on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for CD4041UBF3A reliable?
The price and inventory of CD4041UBF3A are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for CD4041UBF3A is usually 5 days.
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CD4041UBF3A orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your CD4041UBF3A order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for CD4041UBF3A?
For technical support, including CD4041UBF3A datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your CD4041UBF3A requirements.
6.How does Aetrix verify that CD4041UBF3A is sourced from the original manufacturer or authorized distributors?
All CD4041UBF3A products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that CD4041UBF3A meets industry standards.
7.What is the process for return or replacement of CD4041UBF3A?
All CD4041UBF3A units undergo pre-shipment inspection (PSI). If there is an issue with CD4041UBF3A, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The CD4041UBF3A part is unused and in its original packaging.
Return procedure for CD4041UBF3A:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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