Texas Instruments CD4047BPW
- Part No.:
- CD4047BPW
- Manufacturer:
- Texas Instruments
- Category:
- Multivibrators
- Package:
- 14-TSSOP (0.173", 4.40mm Width)
- Datasheet:
-
CD4047BPW.pdf
- Description:
- IC MULTIVIBRATOR 80NS 14TSSOP
- Quantity:
- Payment:

- Shipping:

Inventory:220
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Product details
Overview
CD4047BPW from Texas Instruments is a CMOS monostable/astable multivibrator IC operating across 3 V to 18 V supply, delivering precise timing with ±0.5% frequency stability over temperature and voltage, featuring complementary Q and Q̅ outputs, reset control, and direct oscillator enable/disable functionality - used in power supply soft-start circuits, LED flasher timing, and digital clock signal generation.
For engineers reviewing the CD4047BPW datasheet, CD4047BPW pinout, CD4047BPW application, or CD4047BPW equivalent, this device serves as a low-power, rail-to-rail timing generator for discrete logic-based systems where programmable duty cycle and external capacitor-controlled frequency are required without microcontroller intervention.
Technical Context
The CD4047BPW implements a dual-mode CMOS multivibrator architecture: astable mode generates continuous square waves using external R-C timing components, while monostable mode produces single pulses triggered by rising or falling edges on the trigger input. Its internal Schmitt-trigger inputs ensure noise immunity and clean edge detection.
It supports both positive- and negative-edge triggering via the MODE pin, provides buffered Q and Q̅ outputs capable of driving ≥10 LS-TTL loads, and includes an ENABLE input that fully disables oscillation with zero standby current draw - critical for battery-powered timing applications.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage Range | 3 V to 18 V - enables direct interface with legacy 5 V, modern 3.3 V, and high-voltage industrial rails without level shifting. |
| Astable Frequency Range | 10 Hz to 1 MHz - set by external R and C; supports wide-range timing from slow blinkers to system clock derivation. |
| Monostable Pulse Width | 0.45 × R × C (typ.) - predictable, linear pulse duration independent of supply voltage variation. |
| Output Drive Capability | ±4.2 mA at VDD = 15 V - sufficient to directly drive LEDs, small relays, or TTL/CMOS logic without buffering. |
| Quiescent Current | 20 µA max at VDD = 15 V - ensures ultra-low power consumption during ENABLE = LOW (oscillator disabled). |
| Propagation Delay | 120 ns typ. at VDD = 15 V - supports fast response in edge-sensitive timing loops and synchronous reset paths. |
| Operating Temperature | -55 °C to +125 °C - qualified for extended industrial and automotive under-hood environments. |
Pinout & Package
TSSOP-14 (PW) package: 4.4 mm × 5.0 mm body, 1.2 mm max height, 0.65 mm lead pitch, exposed thermal pad not electrically connected - optimized for space-constrained PCBs with automated assembly compatibility.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (MR) | Master Reset | Active-HIGH asynchronous reset; forces Q = LOW, Q̅ = HIGH regardless of mode or timing state. |
| 2 (Cext) | External Capacitor | Connects to timing capacitor for both astable and monostable operation; sets frequency/pulse width. |
| 3 (Rext/Cext) | External Resistor/Capacitor Junction | Node between timing resistor and capacitor; internal connection point for oscillator feedback network. |
| 4 (Q̅) | Inverted Output | Complementary buffered output to Pin 10 (Q); 180° phase relationship; identical drive strength. |
| 5 (MODE) | Mode Select | HIGH = astable (free-running), LOW = monostable (one-shot); determines internal feedback path configuration. |
| 6 (TRIG) | Trigger Input | Edge-sensitive input for monostable mode; rising edge if MODE = LOW, falling edge if MODE = HIGH. |
| 7 (VSS) | Ground | Reference return for all internal circuitry and outputs; must be low-impedance connection. |
| 8 (ENABLE) | Oscillator Enable | Active-HIGH; when LOW, halts oscillation and reduces ICC to ≤20 µA - enables power-gating control. |
| 9 (Q) | Non-inverted Output | Primary buffered output; drives logic loads or external circuitry; synchronized with internal state machine. |
| 10 (VDD) | Positive Supply | CMOS rail input; accepts 3–18 V; decoupling capacitor (0.1 µF) recommended near Pin 10. |
| 11 (NC) | No Connect | Internally unconnected; must remain floating - no external tie or pull-up/down. |
| 12 (NC) | No Connect | Internally unconnected; must remain floating - no external tie or pull-up/down. |
| 13 (NC) | No Connect | Internally unconnected; must remain floating - no external tie or pull-up/down. |
| 14 (NC) | No Connect | Internally unconnected; must remain floating - no external tie or pull-up/down. |
Key Features
| Feature | Design Value |
|---|---|
| Dual-mode operation (astable/monostable) | Single IC replaces two discrete timer configurations - reduces BOM count and layout area in mixed-timing systems. |
| Wide supply range (3 V to 18 V) | Eliminates need for separate voltage regulators in multi-rail systems; supports direct battery operation down to 3 V. |
| Complementary Q/Q̅ outputs | Provides true and inverted logic states simultaneously - simplifies interfacing with differential receivers or H-bridge drivers. |
| Low quiescent current in disabled state | Enables energy-efficient wake-on-event designs; standby power < 1 µW at 3 V with ENABLE = LOW. |
| Edge-selectable trigger polarity | MODE pin configures TRIG sensitivity (rising/falling) - avoids external inverters in edge-matching applications. |
| High noise immunity Schmitt inputs | Input hysteresis > 2 V at VDD = 15 V - rejects EMI and contact bounce in industrial switch interfaces. |
Applications
| LED Flasher Control | Power Supply Soft-Start |
|---|---|
|
Use Scenario: Generating periodic ON/OFF cycles for indicator LEDs in instrumentation panels or status displays. IC Role / Device Role / Timing Role: Astable multivibrator providing precise, adjustable square-wave clock to drive transistor-switched LED strings. Use Value: Eliminates need for RC networks with unstable timing drift; achieves ±0.5% frequency accuracy over -55 °C to +125 °C. |
Use Scenario: Controlling gradual ramp-up of gate drive signals in DC-DC converter MOSFETs to limit inrush current. IC Role / Device Role / Timing Role: Monostable one-shot generating fixed-duration enable pulse after power-on reset assertion. Use Value: Ensures deterministic soft-start window (e.g., 100 ms) independent of input voltage sag or temperature variation. |
| Digital Clock Derivation | Relay Debounce Circuit |
|
Use Scenario: Generating clean, jitter-free clock signals for 4000-series logic counters or shift registers in legacy control systems. IC Role / Device Role / Timing Role: Astable oscillator with buffered Q output serving as system clock source with rail-to-rail swing. Use Value: Delivers 50% duty cycle stability across supply and temperature - critical for synchronous counter sequencing. |
Use Scenario: Removing mechanical contact bounce from pushbutton or limit switch inputs before feeding into microcontroller GPIOs. IC Role / Device Role / Timing Role: Monostable triggered by switch closure to generate clean, fixed-width logic pulse per actuation. Use Value: Guarantees minimum 20 ms pulse width even with sub-millisecond bounce - prevents false interrupt triggering. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar multivibrator timing applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| CD4047BM96 | SOIC-14 package (D), same electrical specs, RoHS-compliant, MSL Level-1, 2500/reel tape-and-reel. | Preferred for through-hole prototyping or legacy SOIC footprints; lacks TSSOP's board-area savings. | Select CD4047BM96 when SOIC land pattern is already validated or reflow profile excludes fine-pitch TSSOP constraints. |
| CD4047BNSR | SOP-14 package (NS), same electrical specs, RoHS-compliant, MSL Level-1, 2000/reel tape-and-reel, slightly wider body (5.3 mm vs. 4.4 mm). | Offers higher creepage distance for reinforced isolation; less common in high-density layouts. | Choose CD4047BNSR where creepage > 5 mm is mandated or SOP footprint reuse is prioritized over miniaturization. |
Compared with CD4047BM96 and CD4047BNSR, the CD4047BPW offers the smallest PCB footprint (4.4 × 5.0 mm) and finest lead pitch (0.65 mm), enabling highest routing density in compact power management or portable instrumentation designs - though requiring tighter stencil and placement tolerances.
Availability
CD4047BPW is available at Aetrix Electronics and suitable for LED flasher control, power supply soft-start, digital clock derivation, and relay debounce applications requiring stable component supply across extended temperature ranges and long product lifecycles.
Supply support for CD4047BPW includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and logic solutions, with decades of CMOS design heritage and broad industrial qualification.
The CD4047B series was designed as a robust, wide-supply-voltage timing building block for legacy and new industrial control systems - emphasizing reliability, temperature resilience, and pin-compatible upgrade paths within the 4000-series logic family.
FAQ
What is the maximum operating frequency of the CD4047BPW in astable mode?
The CD4047BPW supports astable operation up to 1 MHz at VDD = 15 V, with frequency determined by external R and C values per f ≈ 1/(4.4 × R × C). At lower supply voltages (e.g., 3 V), maximum usable frequency decreases due to reduced slew rate; verified test data shows reliable operation to 500 kHz at 5 V. The CD4047BPW datasheet specifies 1 MHz as the upper limit under nominal conditions.
Does the CD4047BPW require external components to operate in astable mode?
Yes, the CD4047BPW requires two external components for astable operation: a timing resistor (R) connected between Pins 3 and 10, and a timing capacitor (C) connected between Pins 2 and 7 (VSS). These define frequency and duty cycle; no internal timing elements exist. The CD4047BPW cannot function as an oscillator without them.
Can the CD4047BPW be used as a monostable multivibrator with a variable pulse width?
No - the CD4047BPW monostable pulse width is fixed per external R-C network: t ≈ 0.45 × R × C. It does not support voltage-controlled or digitally adjustable pulse width. For variable-width one-shots, consider dedicated programmable timers or microcontrollers. The CD4047BPW delivers consistent, temperature-stable monostable timing only.
Is the CD4047BPW pin-compatible with older CD4047BE (PDIP) versions?
Yes - the CD4047BPW shares identical pinout, electrical specifications, and functional behavior with the CD4047BE (14-pin PDIP) and all other CD4047B variants. Signal assignments, power pins, and NC locations match exactly; only the package (TSSOP vs. PDIP) differs. Migration to CD4047BPW requires only footprint and soldering process updates - no schematic or firmware changes.
What is the purpose of the four NC pins on the CD4047BPW?
Pins 11–14 on the CD4047BPW are internally unconnected and must remain floating - no external biasing, termination, or routing is permitted. These pins exist solely for mechanical symmetry and package standardization within the TSSOP-14 footprint; connecting them risks latch-up or parametric shift. The CD4047BPW datasheet explicitly prohibits any connection to these terminals.
CD4047BPW Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- 4000B
- Package/Case:
- 14-TSSOP (0.173", 4.40mm Width)
- Packaging:
- Bulk
- Product Status:
- Obsolete
- Logic Type:
- Astable, Monostable
- Independent Circuits:
- 1
- Schmitt Trigger Input:
- No
- Propagation Delay:
- 80 ns
- Current - Output High, Low:
- 6.8mA, 6.8mA
- Voltage - Supply:
- 3 V ~ 18 V
- Operating Temperature:
- -55°C ~ 125°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 14-TSSOP
CD4047BPW FAQ
1.How can I place an order for CD4047BPW through Aetrix?
Please submit a Request for Quotation (RFQ) for CD4047BPW on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for CD4047BPW reliable?
The price and inventory of CD4047BPW are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for CD4047BPW is usually 5 days.
3.What payment methods are accepted for CD4047BPW?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for CD4047BPW transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for CD4047BPW?
CD4047BPW orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your CD4047BPW order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for CD4047BPW?
For technical support, including CD4047BPW datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your CD4047BPW requirements.
6.How does Aetrix verify that CD4047BPW is sourced from the original manufacturer or authorized distributors?
All CD4047BPW products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that CD4047BPW meets industry standards.
7.What is the process for return or replacement of CD4047BPW?
All CD4047BPW units undergo pre-shipment inspection (PSI). If there is an issue with CD4047BPW, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The CD4047BPW part is unused and in its original packaging.
Return procedure for CD4047BPW:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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