Texas Instruments CD4054BMT
- Part No.:
- CD4054BMT
- Manufacturer:
- Texas Instruments
- Category:
- Display Drivers
- Package:
- 16-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
CD4054BMT.pdf
- Description:
- IC DRVR 4 SEGMENT 16SOIC
- Quantity:
- Payment:

- Shipping:

Inventory:3,821
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
CD4054BMT from Texas Instruments is a CMOS BCD-to-7-segment latch/decoder driver IC designed for direct LED segment control in digital displays. It accepts 4-bit BCD input, latches data, decodes to seven active-low segment outputs (a–g), and features blanking and phase control inputs for multiplexed display timing. Operates over −55°C to +125°C with supply voltage range 3 V to 18 V, supporting industrial panel meters and legacy instrumentation.
For engineers reviewing the CD4054BMT datasheet, CD4054BMT pinout, CD4054BMT application, or CD4054BMT equivalent, key selection criteria include its active-low open-drain segment outputs, built-in latch functionality, BCD-only decoding (no hexadecimal support), wide VDD tolerance, and compatibility with common-cathode LED displays in high-reliability embedded systems.
Technical Context
The CD4054BMT implements synchronous latching followed by static BCD-to-7-segment decoding, with separate BL (blanking) and PH (phase) inputs enabling time-multiplexed display driving. Its output stage uses buffered open-drain NMOS transistors capable of sinking ≥10 mA per segment at VDD = 15 V.
All logic functions operate within standard CMOS voltage thresholds, with input hysteresis on BL and PH for noise immunity. The device lacks internal current limiting, requiring external series resistors for LED current control, and does not support TTL-level inputs or 3.3-V logic interfacing without level translation.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Logic Family | CMOS - ensures low static power consumption and high noise immunity in noisy industrial environments |
| Supply Voltage Range | 3 V to 18 V - supports direct battery or unregulated rail operation without external regulators |
| Output Type | Active-low open-drain - requires external pull-up to VDD or separate segment supply for LED anode biasing |
| Segment Drive Capability | ≥10 mA sink per output at VDD = 15 V - sufficient for standard 0.5-inch LED segments with 330 Ω series resistors |
| Input Compatibility | CMOS-level only - inputs swing from 0 V to VDD; not 5-V TTL compatible without interface circuitry |
| Operating Temperature | −55°C to +125°C - qualified for extended industrial and aerospace-grade applications |
Pinout & Package
CD4054BMT is supplied in a 16-pin SOIC (D) package, 3.9 mm body width, 1.75 mm height, with 0.65 mm lead pitch and RoHS-compliant NiPdAu lead finish. Moisture sensitivity level is Level-1 (unlimited floor life at ≤30°C/60% RH).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (A) | BCD Input A (LSB) | Least-significant BCD bit; must be driven to defined logic level to avoid undefined decode state |
| 2 (B) | BCD Input B | Second BCD bit; no internal pull-up/pull-down - floating input invalid |
| 3 (C) | BCD Input C | Third BCD bit; part of synchronous 4-bit latch - changes sampled only on rising clock edge |
| 4 (D) | BCD Input D (MSB) | Most-significant BCD bit; determines digit value 0–9; values 10–15 yield blanked output |
| 5 (BL) | Blanking Input | Active-low; forces all segment outputs high-impedance when asserted - used for display dimming or digit blanking |
| 6 (PH) | Phase Input | Controls polarity of decoded outputs; toggling enables alternating common-cathode/anode multiplexing schemes |
| 7 (CLK) | Strobe/Clock Input | Rising-edge triggered latch - captures BCD inputs and holds until next strobe |
| 8 (VSS) | Ground | Reference for all inputs and outputs; must be low-impedance connection to minimize ground bounce |
| 9 (a) | Segment a Output | Active-low open-drain output for top horizontal LED segment; requires external pull-up |
| 10 (b) | Segment b Output | Active-low open-drain for upper-right vertical segment; shares same drive strength as all segment outputs |
| 11 (c) | Segment c Output | Active-low open-drain for lower-right vertical segment; no internal current limiting |
| 12 (d) | Segment d Output | Active-low open-drain for bottom horizontal segment; sinks current when lit |
| 13 (e) | Segment e Output | Active-low open-drain for lower-left vertical segment; identical electrical specs to other segment outputs |
| 14 (f) | Segment f Output | Active-low open-drain for upper-left vertical segment; must be externally current-limited |
| 15 (g) | Segment g Output | Active-low open-drain for middle horizontal segment; drives center bar of '8' and '0' |
| 16 (VDD) | Positive Supply | Power rail for logic and output stages; bypass capacitor (0.1 µF) required near pin |
Key Features
| Feature | Design Value |
|---|---|
| Latched BCD input | Eliminates need for continuous BCD bus hold during display refresh - reduces microcontroller I/O load and timing constraints |
| Active-low open-drain outputs | Enables flexible LED anode biasing (common-anode or common-cathode) and mixed-voltage segment supplies |
| Blanking and phase control | Supports dynamic multiplexing across multiple digits without external logic or PWM controllers |
| Wide supply range (3–18 V) | Permits direct integration into 5 V, 9 V, 12 V, or 15 V systems without level-shifting or regulation |
| Extended temperature rating | Validated operation from −55°C to +125°C - suitable for avionics, downhole tools, and military chassis |
Applications
| Industrial Panel Meters | Avionics Display Units |
|---|---|
Use Scenario: Driving 7-segment LED displays in analog-to-digital panel meters used for voltage, current, or pressure monitoring in factory control cabinets. IC Role / Device Role / Timing Role: Latch/decoder driver that receives BCD from ADC interface logic and directly sources/sinks LED segment current under microcontroller strobe control. Use Value: Reduces system component count by eliminating discrete transistor drivers and simplifies firmware by offloading BCD-to-segment mapping and blanking sequencing. |
Use Scenario: Digit control in standby attitude indicators or engine parameter displays where reliability and temperature resilience are critical. IC Role / Device Role / Timing Role: Segment driver synchronized to aircraft bus timing via external strobe; BL and PH pins enable flicker-free multiplexing across four-digit displays. Use Value: Meets DO-160 environmental stress requirements due to −55°C to +125°C qualification and CMOS radiation tolerance. |
| Legacy Test Equipment | Energy Meter Displays |
Use Scenario: Retrofitting aging benchtop multimeters and signal generators with modern LED displays while retaining original TTL/CMOS control logic. IC Role / Device Role / Timing Role: BCD decoder interface between vintage microcode and new LED modules; PH pin adapts to existing phase-clock signals. Use Value: Enables drop-in replacement of obsolete 7447/7448 without redesigning PCB layout or firmware timing. |
Use Scenario: Driving 4-digit kWh readouts in utility-grade electricity meters operating continuously in outdoor enclosures. IC Role / Device Role / Timing Role: Latched segment driver receiving BCD from metrology SoC; BL input supports tariff-based display dimming during off-peak hours. Use Value: Delivers >10-year operational life at elevated ambient temperatures due to proven CMOS process stability and low leakage. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar BCD-to-7-segment latch/decoder applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| CD4511BE | Active-high TTL-compatible outputs; includes lamp test and ripple blanking inputs; no PH pin | Designed for common-cathode LEDs only; requires 5 V supply; lacks phase control for AC-coupled multiplexing | Select when interfacing with 5 V TTL logic and using fixed-polarity common-cathode displays |
| MC14495P | Open-collector outputs with integrated current-limiting resistors; single-supply 5–15 V; no latch function | Requires continuous BCD update; limited to 5 mA per segment; no blanking or phase control | Select for simple non-multiplexed displays where latch timing adds complexity |
Compared with CD4054BMT, CD4511BE offers TTL input compatibility but sacrifices phase flexibility and wide-voltage operation, while MC14495P simplifies LED biasing yet removes latching and blanking-making CD4054BMT optimal for robust, multiplexed, wide-supply industrial displays.
Availability
CD4054BMT is available at Aetrix Electronics and suitable for industrial panel meters, avionics display units, and legacy test equipment requiring stable component supply and long-term obsolescence management.
Supply support for CD4054BMT includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader founded in 1930, specializing in analog, embedded processing, and logic ICs with emphasis on reliability, longevity, and industrial-grade qualification.
The CD4054BMT belongs to TI's legacy CMOS 4000-series logic family, engineered for high-noise-immunity digital interfacing in harsh environments where wide supply range and extended temperature operation are mandatory.
FAQ
What is the maximum recommended supply voltage for CD4054BMT?
The CD4054BMT is rated for operation up to 18 V DC on VDD. Exceeding this voltage risks permanent damage to the oxide gate structures. For reliable long-term use at elevated temperatures, TI recommends limiting VDD to 15 V when operating above +85°C to maintain parametric margin and reduce leakage current drift in the CD4054BMT.
Does CD4054BMT support hexadecimal (0–F) digit decoding?
No, the CD4054BMT decodes only valid BCD inputs (0–9). Inputs representing decimal 10–15 (1010–1111) result in all segment outputs being forced high-impedance (blanked), regardless of BL or PH state. This behavior is inherent to the CD4054BMT's internal decode logic and cannot be overridden.
Can CD4054BMT drive common-anode LED displays directly?
Yes - the CD4054BMT's active-low open-drain outputs are compatible with common-anode LEDs when used with external pull-up resistors connected to a positive supply (e.g., +5 V or +12 V). The anode of each LED connects to the pull-up rail, and the cathode connects to the CD4054BMT output pin, enabling direct current sinking.
Is CD4054BMT pin-compatible with CD4056BMT?
No - although both are BCD-to-7-segment drivers in SOIC-16 packages, CD4054BMT and CD4056BMT have different pinouts and functional assignments. CD4056BMT features active-high outputs and lacks the PH pin, making them electrically and physically incompatible without PCB redesign. Substitution is not recommended.
What is the purpose of the PH (Phase) input on CD4054BMT?
The PH input on CD4054BMT controls the polarity relationship between segment outputs and display common terminals. When PH = LOW, outputs are inverted relative to PH = HIGH - enabling seamless switching between common-cathode and common-anode multiplexing schemes using the same hardware, without changing external resistor networks or supply rails in the CD4054BMT application.
CD4054BMT Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 16-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Discontinued at Digi-Key
- Display Type:
- LCD
- Configuration:
- 4 Segment
- Interface:
- -
- Digits or Characters:
- -
- Current - Supply:
- 40 nA
- Voltage - Supply:
- 3V ~ 18V
- Operating Temperature:
- -55°C ~ 125°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-SOIC
CD4054BMT FAQ
1.How can I place an order for CD4054BMT through Aetrix?
Please submit a Request for Quotation (RFQ) for CD4054BMT on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for CD4054BMT reliable?
The price and inventory of CD4054BMT are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for CD4054BMT is usually 5 days.
3.What payment methods are accepted for CD4054BMT?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for CD4054BMT transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for CD4054BMT?
CD4054BMT orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your CD4054BMT order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for CD4054BMT?
For technical support, including CD4054BMT datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your CD4054BMT requirements.
6.How does Aetrix verify that CD4054BMT is sourced from the original manufacturer or authorized distributors?
All CD4054BMT products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that CD4054BMT meets industry standards.
7.What is the process for return or replacement of CD4054BMT?
All CD4054BMT units undergo pre-shipment inspection (PSI). If there is an issue with CD4054BMT, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The CD4054BMT part is unused and in its original packaging.
Return procedure for CD4054BMT:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
CD4054BMT Tags

-
PCA8561AHN/AY
NXP Semiconductors

-
SN74LS47N
Texas Instruments

-
PCF85176T/1Y
NXP Semiconductors

-
PCF85176H/1,518
NXP Semiconductors

-
BU9796AMUV-E2
Rohm Semiconductor

-
PCA85176H/Q900/1,5
NXP Semiconductors

-
PCF8537AH/1,518
NXP Semiconductors

-
LM3914VX/NOPB
Texas Instruments

-
PCF85134HL/1,118
NXP Semiconductors

-
AS1115-BSST
ams-OSRAM USA INC.

-
PCA8534AH/Q900/1,5
NXP Semiconductors

-
LM3914V/NOPB
Texas Instruments
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
