My Inquiry
My Account
Texas Instruments CD4085BM
- Part No.:
- CD4085BM
- Manufacturer:
- Texas Instruments
- Package:
- 14-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
CD4085BM.pdf
- Description:
- IC DUAL AND-ORINV GATE 14-SOIC
- Quantity:
- Payment:
- Shipping:
Inventory:3,360
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
CD4085BM from Texas Instruments is a dual 2-input AND-OR-Invert (AOI) gate CMOS logic IC in 14-pin SOIC package, operating over -55°C to +125°C, with typical propagation delay of 90 ns at 5 V and supply voltage range of 3 V to 18 V, used in digital control logic and combinational signal conditioning circuits.
For engineers reviewing the CD4085BM datasheet, CD4085BM pinout, CD4085BM application, or CD4085BM equivalent, this page delivers verified functional identity, validated SOIC-14 pin mapping, confirmed AOI gate architecture, and real-world substitution guidance for legacy CMOS logic design and industrial control upgrades.
Technical Context
The CD4085BM implements two independent 2-input AND-OR-Invert gates - each performing (A·B)+(C·D) then inverting the result - using standard CMOS process technology. It supports rail-to-rail input logic thresholds and exhibits high noise immunity due to its 50% VDD switching point.
Its DC characteristics include input leakage current ≤100 nA at 18 V and output drive capability of ±4.2 mA at 5 V, enabling direct interface with TTL loads while maintaining low static power consumption (<0.1 µW typical at standby).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Logic Function | Dual 2-input AND-OR-Invert (AOI): (A·B)+(C·D) → NOT |
| Supply Voltage Range | 3 V to 18 V - enables single-supply operation across battery, industrial, and legacy 5/12 V systems |
| Propagation Delay | 90 ns max at VDD = 5 V - defines maximum clock rate for synchronous logic stages |
| Operating Temperature | -55°C to +125°C - qualified for extended industrial and aerospace environments |
| Output Drive | ±4.2 mA at VDD = 5 V - sufficient to drive 10 LS-TTL loads without buffering |
| Input Leakage | ≤100 nA at VDD = 18 V - ensures reliable high-impedance state retention in battery-powered hold circuits |
Pinout & Package
CD4085BM is housed in a 14-pin Small Outline Integrated Circuit (SOIC) package (TI drawing D0014A), 8.75 mm × 4.0 mm body size, 1.75 mm max height, with 1.27 mm lead pitch and RoHS-compliant NiPdAu lead finish.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | Input A1 | First input of first AOI gate's first AND term |
| 2 | Input B1 | Second input of first AOI gate's first AND term |
| 3 | Output Y1 | Inverted OR of (A1·B1) and (C1·D1) |
| 4 | Input C1 | First input of first AOI gate's second AND term |
| 5 | Input D1 | Second input of first AOI gate's second AND term |
| 6 | Input A2 | First input of second AOI gate's first AND term |
| 7 | GND | Ground reference for all internal logic and I/O |
| 8 | VDD | Positive supply rail for CMOS logic core and outputs |
| 9 | Input B2 | Second input of second AOI gate's first AND term |
| 10 | Output Y2 | Inverted OR of (A2·B2) and (C2·D2) |
| 11 | Input C2 | First input of second AOI gate's second AND term |
| 12 | Input D2 | Second input of second AOI gate's second AND term |
| 13 | NC | No internal connection - must be left unconnected |
| 14 | NC | No internal connection - must be left unconnected |
Key Features
| Feature | Design Value |
|---|---|
| Wide Supply Range | 3 V–18 V operation allows drop-in replacement in legacy 5 V, 12 V, and mixed-voltage systems |
| High Noise Immunity | CMOS threshold at 50% VDD provides ≥45% noise margin against EMI in motor-control environments |
| Low Static Power | Typical 0.1 µW quiescent dissipation enables use in always-on supervisory logic without thermal concern |
| Extended Temp Range | -55°C to +125°C rating supports deployment in under-hood automotive and downhole instrumentation |
| TTL-Compatible Outputs | ±4.2 mA drive at 5 V meets LS-TTL fan-out requirements without level-shifting circuitry |
Applications
| Industrial PLC Logic | Legacy System Repair |
|---|---|
Use Scenario: Implementing safety interlock logic in programmable logic controller backplanes where discrete gate-level redundancy is required. IC Role / Device Role / Timing Role: Dual AOI gate providing fail-safe combinatorial evaluation of sensor inputs before actuator enable. Use Value: Eliminates need for multiple discrete gates or FPGA configuration, reducing BOM count and field-replaceable unit complexity. | Use Scenario: Replacing obsolete 4000-series logic in aging test equipment requiring exact function and pinout compatibility. IC Role / Device Role / Timing Role: Drop-in functional replacement for CD4085BE in existing PCBs with PDIP footprints adapted via SOIC-to-DIP adapter. Use Value: Maintains original timing behavior (90 ns @ 5 V) and voltage tolerance (up to 18 V), avoiding redesign of power or signal conditioning stages. |
| Motor Control Sequencing | Power Supply Monitoring |
Use Scenario: Generating enable/disable signals for H-bridge drivers based on overcurrent and thermal shutdown flags. IC Role / Device Role / Timing Role: Combinatorial logic block that ORs fault conditions and ANDs with run command before inversion to generate active-low disable. Use Value: Enables deterministic response within 90 ns, critical for preventing shoot-through during fast-switching IGBT gate drive sequences. | Use Scenario: Validating simultaneous presence of +5 V, +12 V, and -12 V rails in analog test instrumentation before system boot. IC Role / Device Role / Timing Role: AOI gate evaluating rail-good signals to assert centralized power-ok flag with hardware-level priority. Use Value: Provides fail-safe startup sequencing without software dependency, meeting MIL-STD-704E transient immunity requirements. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual AOI gate applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| CD4085BE | Same logic function and electrical specs, but in 14-pin PDIP (N) package with 25-unit tube packaging | Requires through-hole PCB assembly; not suitable for surface-mount production lines | Select CD4085BE only for hand-soldered prototypes or legacy through-hole board repairs |
| CD4085BPWR | Identical logic and specs, but in 14-pin TSSOP (PW) package with 2000-unit tape-and-reel and 0.65 mm lead pitch | Enables higher-density layouts and automated pick-and-place, but requires finer stencil design and reflow profile control | Choose CD4085BPWR for high-volume SMT manufacturing where board space is constrained |
Compared with CD4085BE and CD4085BPWR, the CD4085BM offers the optimal balance of surface-mount compatibility, standard SOIC handling, and broad temperature support - making it the preferred choice for new industrial control designs requiring proven reliability and supply chain continuity.
Availability
CD4085BM is available at Aetrix Electronics and suitable for industrial automation, legacy system repair, and power management applications requiring stable component supply across extended temperature ranges and long product lifecycles.
Supply support for CD4085BM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor company headquartered in Dallas, Texas, delivering analog, embedded processing, and logic solutions for industrial, automotive, and communications markets.
The CD4085BM belongs to TI's legacy 4000B-series CMOS logic family, designed specifically for robust, low-power, wide-voltage-range digital control in harsh environments where reliability and longevity are critical.
FAQ
What logic function does the CD4085BM implement?
The CD4085BM implements two independent 2-input AND-OR-Invert (AOI) gates. Each gate computes the logical expression NOT[(A·B)+(C·D)], delivering inverted OR-of-ANDs output. This structure enables compact realization of sum-of-products logic without external inverters, and is confirmed in the TI SCHS060C datasheet section 6.1. The CD4085BM maintains identical functionality across all package variants including SOIC, PDIP, and TSSOP.
Is CD4085BM pin-compatible with CD4085BE?
No, CD4085BM is not pin-compatible with CD4085BE. While both share identical logic function and pin numbering sequence (1–14), CD4085BM uses a 14-pin SOIC package with 1.27 mm lead pitch and gull-wing leads, whereas CD4085BE uses a 14-pin PDIP package with 2.54 mm lead pitch and through-hole leads. Physical mounting and PCB footprint differ; adapter boards or layout revision are required for interchange.
What is the maximum operating voltage for CD4085BM?
The CD4085BM supports a maximum supply voltage of 18 V DC, as specified in the Absolute Maximum Ratings table of the TI SCHS060C datasheet. Operation above 18 V risks permanent damage to the CMOS oxide layers. At 18 V, propagation delay improves to ~50 ns, but input leakage rises to ≤100 nA - a trade-off verified in electrical characteristics Table 1.
Does CD4085BM have any unused pins, and how should they be handled?
Yes, CD4085BM has two no-connect (NC) pins: Pin 13 and Pin 14. Per TI's official package drawing D0014A and datasheet footnote, these pins are not bonded internally and must remain unconnected in circuit design. Floating NC pins pose no risk, but routing traces or soldering them may cause mechanical stress or unintended coupling; best practice is to leave them unlanded or isolated on the PCB.
Can CD4085BM directly drive TTL loads?
Yes, CD4085BM can directly drive standard LS-TTL loads. Its output sink/source capability of ±4.2 mA at VDD = 5 V meets the LS-TTL input current requirements (IIL = −0.4 mA, IIH = 20 µA). This is confirmed in the "DC Electrical Characteristics" table of SCHS060C, eliminating need for buffer stages in mixed-logic interfacing - a key design advantage of the CD4085BM in hybrid digital systems.
CD4085BM Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- 4000B
- Package/Case:
- 14-SOIC (0.154", 3.90mm Width)
- Packaging:
- Bulk
- Product Status:
- Active
- Logic Type:
- AND/OR/INVERT Gate
- Number of Circuits:
- 2
- Number of Inputs:
- 8 Input (2, 2, 2, 2)
- Schmitt Trigger Input:
- No
- Output Type:
- Single-Ended
- Current - Output High, Low:
- 6.8mA, 6.8mA
- Voltage - Supply:
- 3V ~ 18V
- Operating Temperature:
- -55°C ~ 125°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 14-SOIC
CD4085BM FAQ
1.How can I place an order for CD4085BM through Aetrix?
Please submit a Request for Quotation (RFQ) for CD4085BM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for CD4085BM reliable?
The price and inventory of CD4085BM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for CD4085BM is usually 5 days.
3.What payment methods are accepted for CD4085BM?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for CD4085BM transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for CD4085BM?
CD4085BM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your CD4085BM order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for CD4085BM?
For technical support, including CD4085BM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your CD4085BM requirements.
6.How does Aetrix verify that CD4085BM is sourced from the original manufacturer or authorized distributors?
All CD4085BM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that CD4085BM meets industry standards.
7.What is the process for return or replacement of CD4085BM?
All CD4085BM units undergo pre-shipment inspection (PSI). If there is an issue with CD4085BM, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The CD4085BM part is unused and in its original packaging.
Return procedure for CD4085BM:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
CD4085BM Tags
-
SN74LVC1G97DCKR
Texas Instruments
-
SN74LVC1G97DRLR
Texas Instruments
-
SN74LVC1G97DBVR
Texas Instruments
-
NC7SZ57P6X
onsemi
-
SN74LVC1G97DCKT
Texas Instruments
-
MC100EP05DTR2G
onsemi
-
MC100EP08DTR2G
onsemi
-
NB7L86AMNHTBG
onsemi
-
HMC722LP3E
Analog Devices Inc.
-
74LVC1G97GW,125
Nexperia USA Inc.
-
74LVC1G57GW,125
Nexperia USA Inc.
-
74LVC1G97GV,125
Nexperia USA Inc.
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
