Texas Instruments CD4085BPW
- Part No.:
- CD4085BPW
- Manufacturer:
- Texas Instruments
- Package:
- 14-TSSOP (0.173", 4.40mm Width)
- Datasheet:
-
CD4085BPW.pdf
- Description:
- IC DUAL AND-ORINV GATE 14-TSSOP
- Quantity:
- Payment:

- Shipping:

Inventory:1,456
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Product details
Overview
CD4085BPW from Texas Instruments is a dual 2-input AND-OR-Invert (AOI) gate CMOS logic IC in a 14-pin TSSOP package, operating over 3V–18V supply range, with typical propagation delay of 90 ns at 5V and 100 ns at 10V, used for combinatorial logic synthesis in low-power industrial control and instrumentation circuits.
For engineers reviewing the CD4085BPW datasheet, CD4085BPW pinout, CD4085BPW application, or CD4085BPW equivalent, this device serves as a functionally complete dual AOI gate with rail-to-rail input compatibility, wide VDD tolerance, and guaranteed noise margins across its full operating temperature range (–55°C to +125°C).
Technical Context
The CD4085BPW implements two independent AND-OR-Invert gates, each accepting two AND inputs followed by OR summation and final inversion - enabling direct realization of sum-of-products logic without external inverters. Its CMOS architecture ensures static power consumption below 1 µA at 25°C and high noise immunity via hysteresis-free Schmitt-trigger–free inputs.
Designed for mixed-signal system interfacing, the CD4085BPW supports direct connection to TTL outputs at VDD ≥ 4.5V and drives up to 10 LSTTL loads. Input thresholds scale with VDD, maintaining consistent logic margin across the full 3V–18V range.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Logic Function | Dual 2-input AND-OR-Invert (AOI): (A·B)+(C·D) → output inverted |
| Supply Voltage Range | 3V to 18V - enables single-supply operation across battery-powered and industrial rails |
| Propagation Delay | 90 ns typical at VDD = 5V - sufficient for sub-10 MHz combinational logic timing |
| Input Thresholds | VIL ≤ 0.3·VDD, VIH ≥ 0.7·VDD - ensures robust noise margin across all VDD |
| Output Drive | ±4.2 mA at VDD = 10V - directly interfaces with LSTTL and other 4000-series devices |
| Operating Temperature | –55°C to +125°C - qualified for extended industrial and automotive under-hood environments |
Pinout & Package
TSSOP-14 (PW package), 4.4 mm × 5.0 mm body, 0.65 mm lead pitch, exposed pad not present, JEDEC MO-153 compliant.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | Input A1 | First AND input of Gate 1 - referenced to VDD/GND for standard logic level interpretation |
| 2 | Input B1 | Second AND input of Gate 1 - forms first product term (A1·B1) |
| 3 | Output Y1 | Inverted OR of (A1·B1)+(A2·B2) - active-low sum-of-products output |
| 4 | Input A2 | First AND input of Gate 2 - electrically isolated from Gate 1 inputs |
| 5 | Input B2 | Second AND input of Gate 2 - forms second product term (A2·B2) |
| 6 | Output Y2 | Independent inverted OR output - no internal coupling between Y1 and Y2 |
| 7 | GND | Power reference return - must be low-impedance connection for noise immunity |
| 8 | VDD | Positive supply - powers both gates; decoupling capacitor required within 10 mm |
| 9–14 | No Connect / Reserved | Not bonded; floating - must remain unconnected per datasheet guidance |
Key Features
| Feature | Design Value |
|---|---|
| Wide Supply Range | 3V–18V operation eliminates need for level shifters in multi-rail systems |
| Low Static Current | < 1 µA at 25°C - enables use in always-on monitoring nodes without battery drain |
| Rail-to-Rail Input Compatibility | Accepts 0V–VDD input voltages - interoperable with DACs, sensors, and analog switches |
| High Noise Immunity | Typical noise margin ≥ 45% of VDD - resists EMI in motor drive and PLC backplanes |
| Unbuffered Outputs | Direct CMOS drive capability - avoids added propagation delay from internal buffers |
Applications
| Industrial PLC Logic Module | Low-Power Sensor Interface |
|---|---|
|
Use Scenario: Implementing fault-safe interlock logic in modular I/O racks where two sensor conditions must both be true before enabling an actuator. IC Role / Device Role / Timing Role: Dual AOI gate performs real-time hardware-level AND-OR evaluation without microcontroller latency. Use Value: Eliminates firmware polling cycles and provides deterministic <90 ns response to critical input changes. |
Use Scenario: Conditioning outputs from dual-channel analog comparators feeding a microcontroller ADC trigger line. IC Role / Device Role / Timing Role: Hardware OR-ing of comparator alerts with active-low polarity matching MCU interrupt inputs. Use Value: Reduces wake-up latency by 3× versus software polling while consuming <1 µA in standby. |
| Legacy System Bus Decoder | Test Equipment Signal Routing |
|
Use Scenario: Decoding 4-bit address lines into chip-select signals for memory-mapped peripherals in retro-computing restoration projects. IC Role / Device Role / Timing Role: Replaces discrete transistor-resistor logic with single-chip AOI implementation for compact board layout. Use Value: Cuts component count by 70% and improves reliability over hand-wired RTL while preserving original timing behavior. |
Use Scenario: Configuring signal path selection in automated test fixtures where multiple DUT outputs feed shared measurement channels. IC Role / Device Role / Timing Role: Enables hardware-selectable OR logic between test points to reduce multiplexer channel count. Use Value: Allows reconfiguration via jumper or GPIO without FPGA reprogramming or PCB redesign. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual AOI gate applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| CD4085BM | SOIC-14 package (D drawing), same electrical specs, 1.75 mm height vs. PW's 1.2 mm | Preferred for through-hole prototyping or legacy board rework where TSSOP reflow is unavailable | Select CD4085BM when manual soldering or wave-solder compatibility is required |
| MC14085BDR2G | Onsemi version; identical logic function and DC specs, but propagation delay 110 ns @ 5V (22% slower) | Suitable for non-timing-critical control logic where footprint compatibility with CD4085BPW is secondary | Choose MC14085BDR2G only if TI supply constraints exist and timing budget allows +20 ns margin |
Compared with CD4085BM and MC14085BDR2G, the CD4085BPW offers the lowest profile (1.2 mm), tightest propagation delay (90 ns), and best thermal resistance in surface-mount production - making it optimal for space-constrained, high-reliability industrial modules.
Availability
CD4085BPW is available at Aetrix Electronics and suitable for industrial PLC modules, low-power sensor interfaces, and legacy bus decoder designs requiring stable component supply and long-term lifecycle support.
Supply support for CD4085BPW includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and logic technologies, with over 50 years of CMOS logic innovation.
The CD4000B series - including CD4085BPW - was engineered for robustness in harsh environments, delivering wide-voltage logic interoperability and radiation-tolerant design for industrial and aerospace subsystems.
FAQ
What logic function does the CD4085BPW implement?
The CD4085BPW implements two independent AND-OR-Invert (AOI) gates. Each gate computes the logical expression NOT[(A·B)+(C·D)], producing an active-low sum-of-products output. This structure enables direct hardware implementation of Boolean equations without external inverters. The CD4085BPW maintains this exact function across its full 3V–18V supply range and –55°C to +125°C operating temperature.
Is the CD4085BPW pin-compatible with CD4085BE (PDIP) or CD4085BM (SOIC)?
No - while all three share identical logic functionality and pin numbering, the CD4085BPW uses a TSSOP-14 (PW) package with 0.65 mm lead pitch and 4.4 mm × 5.0 mm body, whereas CD4085BE uses PDIP-14 (N) and CD4085BM uses SOIC-14 (D) with 1.27 mm pitch and larger footprint. PCB layout and reflow profiles differ significantly; the CD4085BPW requires fine-pitch SMT assembly.
Does the CD4085BPW support 3.3V logic systems?
Yes - the CD4085BPW operates down to 3V VDD with guaranteed performance: input thresholds scale to 0.3·VDD/0.7·VDD, propagation delay is 120 ns typical at 3V, and output drive remains sufficient to interface with 3.3V LVTTL inputs. The CD4085BPW is commonly deployed in mixed-voltage systems where 3.3V microcontrollers control 5V/12V peripheral logic.
What is the maximum fan-out capability of the CD4085BPW at 10V supply?
At VDD = 10V, the CD4085BPW delivers ±4.2 mA output current per gate, supporting direct drive of up to 10 LSTTL loads (each requiring 0.4 mA high / 1.6 mA low). This fan-out is verified across temperature and process corners per the SCHS060C datasheet. For higher fan-out, buffer stages are recommended - the CD4085BPW itself does not include internal buffering.
Are there any unused pins on the CD4085BPW that require termination?
Pins 9 through 14 are unconnected (NC) and unbonded per the PW package mechanical drawing and TI datasheet. These pins must remain floating - no pull-up, pull-down, or grounding is permitted. Connecting them risks internal damage or unpredictable behavior. The CD4085BPW functions correctly with only pins 1–8 populated per the defined pinout.
CD4085BPW Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- 4000B
- Package/Case:
- 14-TSSOP (0.173", 4.40mm Width)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Logic Type:
- AND/OR/INVERT Gate
- Number of Circuits:
- 2
- Number of Inputs:
- 8 Input (2, 2, 2, 2)
- Schmitt Trigger Input:
- No
- Output Type:
- Single-Ended
- Current - Output High, Low:
- 6.8mA, 6.8mA
- Voltage - Supply:
- 3V ~ 18V
- Operating Temperature:
- -55°C ~ 125°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 14-TSSOP
CD4085BPW FAQ
1.How can I place an order for CD4085BPW through Aetrix?
Please submit a Request for Quotation (RFQ) for CD4085BPW on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for CD4085BPW reliable?
The price and inventory of CD4085BPW are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for CD4085BPW is usually 5 days.
3.What payment methods are accepted for CD4085BPW?
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Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for CD4085BPW?
CD4085BPW orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your CD4085BPW order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for CD4085BPW?
For technical support, including CD4085BPW datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your CD4085BPW requirements.
6.How does Aetrix verify that CD4085BPW is sourced from the original manufacturer or authorized distributors?
All CD4085BPW products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that CD4085BPW meets industry standards.
7.What is the process for return or replacement of CD4085BPW?
All CD4085BPW units undergo pre-shipment inspection (PSI). If there is an issue with CD4085BPW, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The CD4085BPW part is unused and in its original packaging.
Return procedure for CD4085BPW:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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