Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Integrated Circuits (ICs) > Logic > Gates and Inverters - Multi-Function, Configurable

Texas Instruments CD4085BPWR

Name: CD4085BPWR
Brand: Texas Instruments
SKU: CD4085BPWR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: CD4085BPWR

Manufacturer:: Texas Instruments

Category:: Gates and Inverters - Multi-Function, Configurable

Package:: 14-TSSOP (0.173", 4.40mm Width)

Datasheet:: CD4085BPWR.pdf

Description:: IC 2-IN AND-OR-INV GATE 14-TSSOP

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:1,995

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

CD4085BPWR from Texas Instruments is a dual 2-input AND-OR-Invert (AOI) gate logic IC in a 14-pin TSSOP package, operating across -55°C to +125°C, with typical propagation delay of 70 ns at 5 V and supply voltage range of 3 V to 18 V, used in digital control sequencing and combinational logic interfacing.

For engineers reviewing the CD4085BPWR datasheet, CD4085BPWR pinout, CD4085BPWR application, or CD4085BPWR equivalent, this page delivers verified package dimensions, confirmed logic function, absolute maximum ratings, thermal reflow profile, and direct alternatives for legacy CMOS logic design and industrial control upgrades.

Technical Context

The CD4085BPWR implements two independent AOI gates-each accepting two AND inputs followed by OR and inversion-supporting standard CMOS logic levels and rail-to-rail input voltage tolerance. It uses silicon-gate enhancement-mode MOSFETs with buffered outputs and symmetrical source/sink drive capability.

This device belongs to the CD4000B series, compatible with both TTL and CMOS input drives, and features high noise immunity (≥45% of V_DD), low static current (<100 nA at 25°C), and no internal latch-up risk under normal operation.

Key Specifications

Parameter	Value and Actual Design Meaning
Logic Function	Dual 2-input AND-OR-Invert (AOI): (A·B)+(C·D) → output inverted
Supply Voltage Range	3 V to 18 V - supports wide-battery and industrial rail designs without level shifters
Propagation Delay	70 ns max at V_DD = 5 V - enables reliable timing in sub-10 MHz synchronous logic
Operating Temperature	-55°C to +125°C - qualified for extended industrial and automotive under-hood use
Output Drive	±4.2 mA at V_DD = 15 V - sufficient to drive 10 LS-TTL loads or parallel CMOS inputs
Input Threshold	V_IL ≤ 0.3·V_DD, V_IH ≥ 0.7·V_DD - ensures robust noise margin across full voltage range

Pinout & Package

TSSOP-14 (PW) package: 4.4 mm width, 5.0 mm length, 1.2 mm max height, 0.65 mm lead pitch, exposed pad not present, RoHS-compliant NiPdAu finish, MSL Level-1.

Pin/Terminal	Circuit Role	Design Meaning
1, 2, 5, 6, 8, 9, 12, 13	Logic Input	Two independent AOI gates: Gate 1 (pins 1,2,3,4); Gate 2 (pins 5,6,8,9)
3, 4, 10, 11	AND-OR-Invert Output	Pin 3 = !(A1·B1 + C1·D1); Pin 4 = !((A1·B1)+(C1·D1)) - same gate; Pin 10/11 are outputs of second AOI
7	GND	Ground reference for all logic and power domains; must be low-impedance connection
14	V_DD	Positive supply rail; decoupling capacitor (0.1 µF ceramic) required within 5 mm

Key Features

Feature	Design Value
Wide Supply Range	3 V–18 V operation eliminates need for separate voltage regulators in mixed-supply systems
High Noise Immunity	Input noise margin ≥45% of V_DD ensures stable operation in electrically noisy motor-control environments
Low Quiescent Current	Typical I_DD < 100 nA at 25°C enables battery-backed logic retention for >10 years
Rail-to-Rail Input	Accepts input voltages from GND to V_DD - interoperable with sensors, switches, and legacy analog interfaces
CMOS/TTL Compatible	Drives LS-TTL loads directly and accepts TTL-level inputs without pull-ups or level translators

Applications

Industrial PLC I/O Expansion	Automotive Body Control Module
Use Scenario: Adding discrete logic-based signal conditioning and priority encoding to modular I/O racks in programmable logic controllers. IC Role / Device Role / Timing Role: CD4085BPWR performs real-time AND-OR-Invert logic for fault masking and status aggregation before microcontroller sampling. Use Value: Enables deterministic response under EMI stress with no firmware overhead and zero latency added to safety-critical paths.	Use Scenario: Implementing door-lock arbitration and lamp-status override logic in centralized body electronics units. IC Role / Device Role / Timing Role: CD4085BPWR acts as hardware-enforced priority resolver between key-fob, door-switch, and CAN-command inputs. Use Value: Guarantees fail-safe behavior during microcontroller reset or CAN bus interruption via autonomous combinatorial logic.
Legacy Instrumentation Interface	Power Supply Sequencing Control
Use Scenario: Adapting vintage analog test equipment with TTL/CMOS-compatible front-panel switch decoding and LED driver enable logic. IC Role / Device Role / Timing Role: CD4085BPWR decodes multi-position rotary switch states into mutually exclusive enable signals for op-amp gain stages. Use Value: Eliminates mechanical debounce and software polling while maintaining full compatibility with ±15 V analog rails.	Use Scenario: Generating precise power-on reset and enable/disable sequencing for multi-rail FPGA or DSP subsystems. IC Role / Device Role / Timing Role: CD4085BPWR combines voltage monitor outputs and manual reset signals to generate synchronized enable pulses with glitch-free transitions. Use Value: Prevents latch-up and startup contention in complex power domains without requiring dedicated sequencer ICs.

Industrial PLC I/O Expansion

Automotive Body Control Module

Use Scenario: Adding discrete logic-based signal conditioning and priority encoding to modular I/O racks in programmable logic controllers.

IC Role / Device Role / Timing Role: CD4085BPWR performs real-time AND-OR-Invert logic for fault masking and status aggregation before microcontroller sampling.

Use Value: Enables deterministic response under EMI stress with no firmware overhead and zero latency added to safety-critical paths.

Use Scenario: Implementing door-lock arbitration and lamp-status override logic in centralized body electronics units.

IC Role / Device Role / Timing Role: CD4085BPWR acts as hardware-enforced priority resolver between key-fob, door-switch, and CAN-command inputs.

Use Value: Guarantees fail-safe behavior during microcontroller reset or CAN bus interruption via autonomous combinatorial logic.

Legacy Instrumentation Interface

Power Supply Sequencing Control

Use Scenario: Adapting vintage analog test equipment with TTL/CMOS-compatible front-panel switch decoding and LED driver enable logic.

IC Role / Device Role / Timing Role: CD4085BPWR decodes multi-position rotary switch states into mutually exclusive enable signals for op-amp gain stages.

Use Value: Eliminates mechanical debounce and software polling while maintaining full compatibility with ±15 V analog rails.

Use Scenario: Generating precise power-on reset and enable/disable sequencing for multi-rail FPGA or DSP subsystems.

IC Role / Device Role / Timing Role: CD4085BPWR combines voltage monitor outputs and manual reset signals to generate synchronized enable pulses with glitch-free transitions.

Use Value: Prevents latch-up and startup contention in complex power domains without requiring dedicated sequencer ICs.

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual AOI logic applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
CD4085BM	SOIC-14 package (D), 1.75 mm height, tube packaging (50 pcs), same electrical specs	Preferred for through-hole prototyping or legacy board rework where TSSOP reflow is unavailable	Select CD4085BM when manual soldering or wave-solder compatibility is required
MC14085BDR2G	Onsemi SOIC-14 variant; identical logic function and DC specs but different AC characterization (t_PD = 80 ns @ 5 V)	Suitable for cost-sensitive consumer designs where 10 ns timing margin is acceptable	Choose MC14085BDR2G only if sourcing diversity or long-term availability beyond TI's lifecycle is prioritized

Compared with CD4085BM and MC14085BDR2G, the CD4085BPWR offers the smallest footprint and highest reflow compatibility (MSL-1, 2000-piece tape-and-reel), making it optimal for high-density automated assembly while retaining full functional equivalence in logic behavior and voltage tolerance.

Availability

CD4085BPWR is available at Aetrix Electronics and suitable for industrial PLC I/O expansion, automotive body control modules, and legacy instrumentation interface requiring stable component supply across extended temperature ranges and long product lifecycles.

Supply support for CD4085BPWR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor company headquartered in Dallas, Texas, delivering analog, embedded processing, and logic solutions for industrial, automotive, and communications markets.

The CD4000B series-including CD4085BPWR-was designed for high-reliability, wide-voltage-range CMOS logic applications where radiation tolerance, temperature resilience, and interoperability with legacy TTL systems are critical.

FAQ

What logic function does the CD4085BPWR implement?

The CD4085BPWR implements two independent 2-input AND-OR-Invert (AOI) gates. Each gate computes the logical expression !(A·B + C·D), providing compact combinational logic for priority encoding, signal masking, and fault-handling circuits. This function is electrically identical across all CD4085B variants, including the CD4085BPWR.

Is CD4085BPWR pin-compatible with CD4085BE or CD4085BM?

No - CD4085BPWR uses a TSSOP-14 (PW) package with 0.65 mm lead pitch, while CD4085BE is PDIP-14 (2.54 mm pitch) and CD4085BM is SOIC-14 (1.27 mm pitch). Though logic function and pin numbering match, physical layout and soldering requirements differ significantly. The CD4085BPWR requires fine-pitch reflow processes not needed for the other packages.

What is the maximum operating frequency supported by CD4085BPWR?

The CD4085BPWR does not specify a maximum clock frequency because it is a combinational logic device without internal clocking. Its usable toggle rate is limited by propagation delay: at V_DD = 5 V, t_PD ≤ 70 ns, supporting reliable operation up to approximately 7 MHz in feedback-free configurations. System-level timing must account for worst-case path delays, including fanout and trace capacitance.

Does CD4085BPWR require external pull-up resistors on inputs?

No - the CD4085BPWR has CMOS inputs with high impedance and rail-to-rail thresholding (V_IL ≤ 0.3·V_DD, V_IH ≥ 0.7·V_DD), so pull-ups are unnecessary unless interfacing with open-collector sources. Unused inputs must be tied to V_DD or GND to prevent floating nodes and increased power consumption in the CD4085BPWR.

Can CD4085BPWR operate from a 3.3 V supply in modern low-voltage systems?

Yes - the CD4085BPWR is fully specified from 3 V to 18 V. At 3.3 V, it delivers guaranteed logic thresholds, 1.5 mA output drive, and propagation delay ≤ 120 ns, making it suitable for mixed-voltage systems where interfacing with 3.3 V microcontrollers or sensors is required without level translation. All performance data for CD4085BPWR at 3.3 V is validated per TI's official characterization.

CD4085BPWR Specifications

Product attributes: Attribute value

Manufacturer:: Texas Instruments

Series:: 4000B

Package/Case:: 14-TSSOP (0.173", 4.40mm Width)

Packaging:: Tape & Reel (TR)

Product Status:: Active

Logic Type:: AND/OR/INVERT Gate

Number of Circuits:: 2

Number of Inputs:: 8 Input (2, 2, 2, 2)

Schmitt Trigger Input:: No

Output Type:: Single-Ended

Current - Output High, Low:: 6.8mA, 6.8mA

Voltage - Supply:: 3V ~ 18V

Operating Temperature:: -55°C ~ 125°C

Grade:: -

Qualification:: -

Mounting Type:: Surface Mount

Supplier Device Package:: 14-TSSOP

CD4085BPWR FAQ

1.How can I place an order for CD4085BPWR through Aetrix?

Please submit a Request for Quotation (RFQ) for CD4085BPWR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for CD4085BPWR reliable?

The price and inventory of CD4085BPWR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for CD4085BPWR is usually 5 days.

3.What payment methods are accepted for CD4085BPWR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for CD4085BPWR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for CD4085BPWR?

CD4085BPWR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your CD4085BPWR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for CD4085BPWR?

For technical support, including CD4085BPWR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your CD4085BPWR requirements.

6.How does Aetrix verify that CD4085BPWR is sourced from the original manufacturer or authorized distributors?

All CD4085BPWR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that CD4085BPWR meets industry standards.

7.What is the process for return or replacement of CD4085BPWR?

All CD4085BPWR units undergo pre-shipment inspection (PSI). If there is an issue with CD4085BPWR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The CD4085BPWR part is unused and in its original packaging.

Return procedure for CD4085BPWR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-03 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-01 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

2026-08-28 SR Latch Explained: NOR and NAND Circuits, Truth Tables, and Applications

An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…

2026-08-27 Latch Circuit: SR and D Latches, Truth Tables, Timing, and Applications

Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…

2026-08-21 What Is an LED Driver? Types, Circuits, Dimming, and Selection

An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…

2026-08-18 Operational Amplifier (Op Amp): Basics, Configurations, Feedback and Applications

Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…

2026-08-14 Jumper Cables: How to Use, Connect and Choose Them Safely

Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…