Texas Instruments CD4572UBPWG4
- Part No.:
- CD4572UBPWG4
- Manufacturer:
- Texas Instruments
- Package:
- 16-TSSOP (0.173", 4.40mm Width)
- Datasheet:
-
CD4572UBPWG4.pdf
- Description:
- IC CMOS HEX GATE 4INV 16-TSSOP
- Quantity:
- Payment:

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Product details
Overview
CD4572UBPWG4 from Texas Instruments is a CMOS hex inverter/buffer IC containing six independent gates: two inverters, two non-inverting buffers, and two dual-input NOR gates - all operating over a 3-V to 18-V supply range with typical propagation delay of 90 ns at 5 V. It serves as a logic-level translator and signal conditioning device in legacy industrial control panels and analog-digital interface circuits.
For engineers reviewing the CD4572UBPWG4 datasheet, CD4572UBPWG4 pinout, CD4572UBPWG4 application, or CD4572UBPWG4 equivalent, key selection criteria include its wide VDD range (3–18 V), rail-to-rail output swing, high noise immunity (>50% VDD), and compatibility with TTL/CMOS mixed-signal systems requiring discrete logic consolidation.
Technical Context
The CD4572UBPWG4 integrates six functionally distinct CMOS logic gates on a single die: two inverters (A/B), two non-inverting buffers (C/D), and two 2-input NOR gates (E/F). Each gate features symmetrical input thresholds and full rail-to-rail output drive capability.
It uses standard 4000-series CMOS process technology with Schmitt-trigger inputs only on the NOR gates (pins 12–13 and 1–2), enabling noise-tolerant digital signal conditioning. Input leakage current is ≤100 nA at 18 V, and quiescent current remains below 1 µA across temperature.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage Range | 3 V to 18 V - supports direct interfacing with 5 V TTL, 12 V industrial sensors, and battery-powered 3.3 V microcontrollers without level shifters. |
| Propagation Delay (tPLH/tPHL) | 90 ns max at VDD = 5 V - enables reliable operation in sub-10 MHz clock distribution and asynchronous control paths. |
| Output Drive Capability | ±4.2 mA at VDD = 15 V - sufficient to directly drive LED indicators, small relays, or multiple 74HC inputs without buffering. |
| Input Threshold Voltage | VIH = 0.5 VDD, VIL = 0.33 VDD - ensures robust noise margin (>1.5 V at 5 V) and predictable switching in noisy environments. |
| Operating Temperature | −55 °C to +125 °C - qualified for extended-temperature industrial and automotive under-hood applications. |
| Static Power Dissipation | <1 µA IDD at VDD = 18 V - enables ultra-low-power standby modes in battery-backed monitoring circuits. |
Pinout & Package
TSSOP-16 (PW) package: 5.0 mm × 4.4 mm body, 0.65 mm lead pitch, 1.2 mm max height, moisture sensitivity level 1, RoHS-compliant NIPDAU finish.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 2 | NOR Gate 1 Inputs | Dual active-low inputs accepting standard CMOS logic levels; Schmitt-triggered for hysteresis. |
| 3 | NOR Gate 1 Output | Active-low open-drain compatible output capable of sinking ≥4.2 mA at 15 V. |
| 4, 5 | NOR Gate 2 Inputs | Second independent Schmitt-triggered NOR pair for noise-immune reset or enable logic. |
| 6 | NOR Gate 2 Output | Isolated output stage with rail-to-rail swing and low output impedance (~120 Ω). |
| 7 | GND | Logic ground reference; must be connected directly to system ground plane for noise immunity. |
| 8 | VDD | Positive supply rail; decoupling capacitor (0.1 µF ceramic) required within 5 mm of this pin. |
| 9 | Inverter A Input | Standard CMOS input with no hysteresis; used for clean digital inversion of clocks or data lines. |
| 10 | Inverter A Output | Full-swing complementary output driving capacitive loads up to 50 pF at 10 MHz. |
| 11 | Buffer C Input | Non-inverting input with identical electrical characteristics to pin 9; used for signal pass-through. |
| 12 | Buffer C Output | Low-propagation-delay buffer output optimized for fanout >10 into 74HC loads. |
| 13 | Inverter B Input | Second inverter input sharing same threshold and drive specs as pin 9. |
| 14 | Inverter B Output | Matched output timing and drive strength to pin 10; supports differential signaling when paired. |
| 15 | Buffer D Input | Final non-inverting input; electrically isolated from other sections except shared VDD/GND. |
| 16 | Buffer D Output | Final buffered output; enables independent signal routing without crosstalk between logic blocks. |
Key Features
| Feature | Design Value |
|---|---|
| Hex-function integration | Combines inverters, buffers, and NOR gates in one TSSOP-16 package - reduces board space by ~60% vs discrete 74HC04/00/125 solutions. |
| Schmitt-trigger NOR inputs | Pins 1–2 and 4–5 include built-in hysteresis (≈1.2 V at 5 V), eliminating external RC filters for slow or noisy switch inputs. |
| Rail-to-rail output swing | Outputs swing within 10 mV of VDD and GND - ensures full logic-level compatibility across mixed-voltage subsystems. |
| Wide supply tolerance | Operates from 3 V to 18 V without configuration - simplifies design reuse across 3.3 V, 5 V, and 12 V platforms. |
| High ESD immunity | ≥2 kV HBM rating per JESD22-A114 - protects against handling damage during manual assembly and field service. |
Applications
| Industrial Control Panel Interface | Legacy System Logic Consolidation |
|---|---|
|
Use Scenario: Converting mechanical switch closures and relay feedback signals into clean CMOS logic levels for PLC input modules. IC Role / Device Role / Timing Role: Signal conditioner and level translator using Schmitt-trigger NOR gates (pins 1–3, 4–6) to debounce switches and invert status signals. Use Value: Eliminates need for external RC debouncing networks and discrete inverters, reducing BOM count by 4–6 components per channel. |
Use Scenario: Replacing obsolete 74C04/74C00/74C125 logic families in aging test equipment and instrumentation. IC Role / Device Role / Timing Role: Drop-in functional replacement providing identical pinout-compatible logic functions with improved noise immunity and wider voltage range. Use Value: Extends product lifecycle without PCB redesign; supports modern 3.3 V MCU interfaces while retaining 12 V actuator control. |
| Analog-Digital Boundary Isolation | Power Sequencing Supervisor |
|
Use Scenario: Isolating ADC reference voltage monitoring and DAC update strobes from noisy digital buses in mixed-signal data acquisition systems. IC Role / Device Role / Timing Role: Non-inverting buffer (pins 11–12, 15–16) provides low-capacitance, high-impedance isolation between analog and digital domains. Use Value: Prevents digital switching noise from coupling into precision analog rails, improving effective resolution by ≥1 LSB. |
Use Scenario: Generating synchronized power-on reset pulses and sequenced enable signals for multi-rail DC/DC converters in embedded controllers. IC Role / Device Role / Timing Role: Inverter pairs (pins 9–10, 13–14) create precise delay chains and edge-triggered monostables using external RC timing. Use Value: Enables deterministic power-up order (e.g., core before I/O) with ±5% timing accuracy over −40 °C to +85 °C. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar hex logic function applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| CD4069UBM96 | Contains six identical inverters only; no buffers or NOR gates; SOIC-16 package with 1.27 mm pitch. | Lacks Schmitt-trigger inputs and non-inverting functionality - unsuitable for switch debouncing or signal pass-through roles. | Select only when pure inversion is required and board layout accommodates larger SOIC footprint. |
| 74AC04SCX | Hex inverter only; 2 V to 6 V supply range; faster (8 ns @ 5 V) but incompatible above 6 V and lacks Schmitt inputs. | Cannot replace CD4572UBPWG4 in 12 V industrial or mixed-voltage systems; requires additional level-shifting circuitry. | Choose for high-speed 3.3/5 V digital-only designs where propagation delay dominates over voltage flexibility. |
Compared with CD4572UBPWG4, CD4069UBM96 offers simpler logic but no functional versatility, while 74AC04SCX delivers speed at the cost of voltage range and noise immunity - making CD4572UBPWG4 uniquely suited for ruggedized, multi-supply legacy interface tasks.
Availability
CD4572UBPWG4 is available at Aetrix Electronics and suitable for industrial control panel interface, legacy system logic consolidation, and analog-digital boundary isolation requiring stable component supply and long-term obsolescence mitigation.
Supply support for CD4572UBPWG4 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and logic ICs, with over 90 years of innovation in industrial, automotive, and communications markets.
The CD4572UBPWG4 belongs to TI's legacy 4000-series CMOS logic family, designed specifically for high-reliability, wide-voltage-range applications in industrial automation, test equipment, and aerospace subsystems.
FAQ
What logic functions does the CD4572UBPWG4 provide?
The CD4572UBPWG4 integrates six distinct logic functions: two inverters (pins 9–10 and 13–14), two non-inverting buffers (pins 11–12 and 15–16), and two dual-input NOR gates (pins 1–2→3 and 4–5→6). All functions operate from a single 3–18 V supply and share common VDD and GND pins. This combination enables compact implementation of mixed logic tasks without external gate arrays - a key advantage of the CD4572UBPWG4 in space-constrained industrial designs.
Does the CD4572UBPWG4 have Schmitt-trigger inputs?
Only the two NOR gate inputs (pins 1–2 and 4–5) feature Schmitt-trigger action with ≈1.2 V hysteresis at 5 V supply, enabling reliable switching from slow or noisy signals like mechanical switches or relay contacts. The inverter and buffer inputs (pins 9, 11, 13, 15) use standard CMOS thresholds without hysteresis. This selective hysteresis is a documented characteristic of the CD4572UBPWG4 and avoids unnecessary complexity in clean-signal paths.
What is the maximum operating temperature for the CD4572UBPWG4?
The CD4572UBPWG4 is rated for continuous operation from −55 °C to +125 °C, verified per TI's qualification standards for extended-temperature industrial applications. This rating applies specifically to the PW (TSSOP-16) package variant and is confirmed in the official TI datasheet SCHS090C. Engineers specifying the CD4572UBPWG4 for under-hood automotive or outdoor industrial enclosures can rely on this full-range performance without derating.
Can the CD4572UBPWG4 drive LEDs directly?
Yes - each output of the CD4572UBPWG4 can sink or source up to 4.2 mA at VDD = 15 V, sufficient to drive standard 2 mA indicator LEDs with appropriate series resistors. For example, a 3.3 kΩ resistor at 12 V yields ~3.3 mA forward current. This capability is explicitly specified in the CD4572UBPWG4 datasheet's "Output Drive Capability" section and eliminates need for external transistor drivers in panel-status applications.
Is the CD4572UBPWG4 pin-compatible with other 4000-series logic ICs?
No - the CD4572UBPWG4 has a unique pin assignment optimized for its mixed-gate functionality and is not pin-compatible with standard hex inverters (e.g., CD4069UB) or NOR gate arrays (e.g., CD4002UB). Its pinout is fixed per the TSSOP-16 package drawing PW0016A and must be implemented as documented in the CD4572UBPWG4 datasheet; attempting drop-in replacement will result in incorrect logic behavior.
CD4572UBPWG4 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- 4000B
- Package/Case:
- 16-TSSOP (0.173", 4.40mm Width)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Logic Type:
- NOR/NAND/INVERT Gate
- Number of Circuits:
- 6
- Number of Inputs:
- 8 Input (1, 1, 2, 2, 1, 1)
- Schmitt Trigger Input:
- No
- Output Type:
- Differential
- Current - Output High, Low:
- 6.8mA, 6.8mA
- Voltage - Supply:
- 3V ~ 18V
- Operating Temperature:
- -55°C ~ 125°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-TSSOP
CD4572UBPWG4 FAQ
1.How can I place an order for CD4572UBPWG4 through Aetrix?
Please submit a Request for Quotation (RFQ) for CD4572UBPWG4 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
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The price and inventory of CD4572UBPWG4 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for CD4572UBPWG4 is usually 5 days.
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5.How can I obtain technical support or documentation for CD4572UBPWG4?
For technical support, including CD4572UBPWG4 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your CD4572UBPWG4 requirements.
6.How does Aetrix verify that CD4572UBPWG4 is sourced from the original manufacturer or authorized distributors?
All CD4572UBPWG4 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that CD4572UBPWG4 meets industry standards.
7.What is the process for return or replacement of CD4572UBPWG4?
All CD4572UBPWG4 units undergo pre-shipment inspection (PSI). If there is an issue with CD4572UBPWG4, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The CD4572UBPWG4 part is unused and in its original packaging.
Return procedure for CD4572UBPWG4:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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