Texas Instruments CD54AC153F3A
- Part No.:
- CD54AC153F3A
- Manufacturer:
- Texas Instruments
- Category:
- Signal Switches, Multiplexers, Decoders
- Package:
- 16-CDIP (0.300", 7.62mm)
- Datasheet:
-
CD54AC153F3A.pdf
- Description:
- DUAL 4-INPUT MULTIPLEXERS 16-CDI
- Quantity:
- Payment:

- Shipping:

Inventory:4,018
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Product details
Overview
CD54AC153F3A from Texas Instruments is a military-grade dual 4-line to 1-line data selector/multiplexer in 16-pin CDIP (J) package, operating from 1.5 V to 5.5 V with ±24 mA output drive, balanced propagation delays, and 2 kV HBM ESD rating. It implements two independent 4:1 multiplexers with separate active-low strobe inputs (1G, 2G), address inputs A/B shared between channels, and supports high-reliability data routing in aerospace and defense timing and control systems.
For engineers reviewing the CD54AC153F3A datasheet, CD54AC153F3A pinout, CD54AC153F3A application, or CD54AC153F3A equivalent, this page delivers verified electrical specs (tPLH/tPHL down to 5 ns at 5 V), thermal metrics (RθJA = 67 °C/W), noise-immune CMOS operation, SCR-latchup resistance, and precise pin-function mapping for layout validation and MIL-STD-883-compliant design integration.
Technical Context
The CD54AC153F3A integrates two independent 4:1 multiplexer sections, each with dedicated active-low strobe (1G/2G), shared binary address inputs (A, B), four data inputs (C0–C3 per channel), and one output (1Y/2Y). Its logic diagram confirms positive-logic decoding via inverters and AND-OR gates, enabling full binary selection without external decoding logic.
It uses SCR-latchup-resistant CMOS process technology and meets MIL-STD-883 requirements for temperature range (−55°C to +125°C), supply voltage (1.5 V to 5.5 V), and ESD immunity (±2000 V HBM). Propagation delay balance across channels and input-to-output paths ensures deterministic timing in synchronous data switching applications.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage | 1.5 V to 5.5 V - enables interoperability with 1.8 V, 3.3 V, and 5 V logic families without level shifters |
| Output Drive | ±24 mA - drives up to 15 F-series loads directly, eliminating need for buffer stages in legacy TTL interfaces |
| Propagation Delay | 5 ns (tPLH/tPHL, VCC = 5 V) - supports >20 MHz data switching in real-time control and test equipment |
| ESD Rating | ±2000 V HBM - exceeds MIL-STD-883 Method 3015, ensuring robustness in handling and board assembly |
| Operating Temp | −55°C to +125°C - qualified for extended-temperature military and avionics environments per QML Class V |
| Power Dissipation Cap | 93 pF - low dynamic power consumption enables use in thermally constrained chassis-mounted modules |
| Input Noise Immunity | 30% of VCC - maintains reliable logic thresholds across wide supply variation, critical for unregulated power rails |
Pinout & Package
CD54AC153F3A is supplied in a 16-pin Ceramic Dual In-line Package (CDIP, J package), body size 19.3 mm × 6.35 mm, with through-hole mounting and SNPB (tin-lead) finish. The package provides hermetic sealing and thermal stability required for high-reliability military applications.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 15 | 1G, 2G - Active-Low Strobe Inputs | Enable/disable respective 4:1 multiplexer section independently; asserted low to pass selected data to output |
| 2, 14 | B, A - Address Select Inputs | Shared binary address lines (A = LSB, B = MSB) selecting C0–C3 on both channels simultaneously |
| 3–6, 10–13 | 1C3–1C0, 2C3–2C0 - Data Inputs | Four parallel data inputs per channel; each pair maps to one 4:1 mux section |
| 7, 9 | 1Y, 2Y - Data Outputs | Active-high outputs reflecting selected input (C0–C3) when corresponding strobe (1G/2G) is low |
| 8 | GND | Ground reference for all internal logic and I/O; must be low-impedance connection in PCB layout |
| 16 | VCC | Positive supply rail; requires local 0.1 µF bypass capacitor per TI layout guidelines |
Key Features
| Feature | Design Value |
|---|---|
| Balanced propagation delays | Matched tPLH/tPHL across channels ensures synchronized data routing in dual-path systems like redundant signal selectors |
| SCR-latchup-resistant CMOS | Prevents destructive latchup under transient overvoltage or ground bounce, essential for MIL-STD-704 aircraft power environments |
| 1.5 V to 5.5 V operation | Single device replaces multiple voltage-specific logic families, simplifying BOM and reducing qualification overhead |
| ±24 mA output drive | Directly interfaces with legacy TTL loads and long traces without external drivers, lowering system component count |
| 2 kV HBM ESD protection | Eliminates need for discrete ESD protection diodes in front-end signal paths, saving board space and cost |
Applications
| Avionics Signal Routing | Military Test Equipment |
|---|---|
|
Use Scenario: Selecting among four sensor inputs (e.g., airspeed, altitude, attitude, temperature) for display or telemetry transmission in flight control computers. IC Role / Device Role / Timing Role: Dual-channel data selector routing analog-to-digital converter outputs to a shared processor bus under software-controlled address and strobe signals. Use Value: Enables time-multiplexed acquisition from redundant sensors while maintaining deterministic latency (<5 ns skew) between channels. |
Use Scenario: Configuring stimulus/response paths in automated test systems that switch between multiple DUTs or calibration references. IC Role / Device Role / Timing Role: Multiplexing digital control signals to different test fixtures using synchronized A/B addressing and independent strobes for isolation. Use Value: Reduces test head cabling complexity and eliminates mechanical relay wear by providing solid-state, sub-10 ns switching. |
| Radar Subsystem Control | Secure Communication Modules |
|
Use Scenario: Routing timing pulses or trigger signals between waveform generators, receivers, and beam-steering logic in phased-array radar front ends. IC Role / Device Role / Timing Role: High-reliability data selector distributing clock-derived triggers across multiple RF chains with matched path delay. Use Value: Maintains phase coherence across parallel processing paths due to balanced propagation characteristics and −55°C to +125°C operation. |
Use Scenario: Managing key selection and data path enablement in cryptographic co-processors where physical tamper resistance is mandatory. IC Role / Device Role / Timing Role: Secure signal gating element controlling access to encryption engine inputs/outputs under strobe-controlled enable conditions. Use Value: Provides hardware-enforced signal isolation with military-grade process reliability and no latchup vulnerability during fault injection. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual 4:1 multiplexer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| CD74AC153E | Commercial-grade PDIP variant; same logic function, pinout, and AC specs but rated −40°C to +85°C and RoHS-compliant (NIPDAU) | Suitable for industrial control and non-military embedded systems; lacks MIL-STD-883 qualification and extended temperature range | Select CD74AC153E for cost-sensitive commercial designs where military temp range and hermetic packaging are unnecessary |
| CD74AC153M96 | SOIC-16 package with same electrical specs; RoHS-compliant, tape-and-reel delivery, MSL Level-1 rating | Preferred for automated SMT assembly and space-constrained PCBs; not suitable for through-hole or high-vibration environments | Choose CD74AC153M96 when surface-mount manufacturing, reflow compatibility, and smaller footprint outweigh hermeticity needs |
Compared with CD54AC153F3A, CD74AC153E offers lower cost and RoHS compliance but sacrifices extended temperature and military qualification, while CD74AC153M96 enables modern SMT production yet lacks the ruggedized CDIP package and −55°C capability required for airborne platforms.
Availability
CD54AC153F3A is available at Aetrix Electronics and suitable for avionics signal routing, military test equipment, radar subsystem control, and secure communication modules requiring stable component supply across extended temperature and high-reliability environments.
Supply support for CD54AC153F3A includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and high-reliability logic solutions, with decades of experience delivering components certified to MIL-STD-883 and QML standards.
The CD54AC153F3A belongs to TI's military AC logic family, designed specifically for high-integrity data selection in aerospace, defense, and critical infrastructure systems where deterministic timing and environmental resilience are mandatory.
FAQ
What is the maximum operating temperature for CD54AC153F3A?
The CD54AC153F3A is fully specified and qualified for continuous operation from −55°C to +125°C, meeting MIL-STD-883 temperature testing requirements. This extended range is enabled by its ceramic DIP (CDIP) package and SCR-latchup-resistant CMOS process, making it suitable for engine-mounted avionics and space-constrained military chassis where ambient temperatures exceed commercial limits. The CD54AC153F3A maintains full functionality-including propagation delay, output drive, and noise immunity-across this entire range.
Does CD54AC153F3A support 3.3 V logic levels?
Yes, CD54AC153F3A fully supports 3.3 V operation with guaranteed performance: at VCC = 3.3 V ± 0.3 V, it delivers tPLH/tPHL ≤ 25.5 ns (−40°C to +85°C) and ≥2.4 V VOH at −4 mA load. Its input thresholds scale with VCC (VIH = 2.1 V, VIL = 0.9 V), ensuring clean interfacing with 3.3 V microcontrollers and FPGAs. The CD54AC153F3A also maintains 30% noise immunity margin and ±24 mA drive capability at this voltage, preserving signal integrity in mixed-voltage systems.
Is CD54AC153F3A pin-compatible with CD74AC153 variants?
Yes, CD54AC153F3A is functionally and pinout-compatible with CD74AC153E (PDIP), CD74AC153M96 (SOIC), and CD74AC153PWR (TSSOP) - all share identical pin numbering, signal names, and logic behavior per TI's SCHS334C datasheet. However, mechanical dimensions, thermal resistance (e.g., RθJA = 67 °C/W for CD54AC153F3A vs. 119.9 °C/W for SOIC), and qualification level differ. The CD54AC153F3A retains the same 16-pin layout but requires through-hole mounting and handles higher thermal stress due to its ceramic construction.
What is the purpose of the separate strobe inputs (1G and 2G) on CD54AC153F3A?
The separate active-low strobe inputs (1G and 2G) on CD54AC153F3A allow independent enable/disable control of each 4:1 multiplexer section. When 1G is low, Channel 1 outputs the selected C0–C3 input based on A/B address; when high, 1Y is forced high-impedance (not high-level). This enables time-multiplexed or conditional routing-for example, using 1G to gate sensor data only during valid sampling windows while holding 2G low to continuously monitor a reference signal. The CD54AC153F3A thus supports asynchronous channel arbitration without external logic.
How does CD54AC153F3A handle unused inputs in a system design?
All unused inputs on CD54AC153F3A-including address lines A/B, strobes 1G/2G, and data inputs C0–C3-must be tied to a defined logic level (VCC or GND) per TI's SCBA004 guidance. Floating inputs cause undefined states, increased ICC current, and potential oscillation due to CMOS input structure. For example, an unused 2G should be pulled high (to VCC) to disable Channel 2, while unused C1/C2 on Channel 1 may be tied to GND. The CD54AC153F3A's SCR-latchup-resistant design tolerates such static biasing without degradation, ensuring long-term reliability in fielded systems.
CD54AC153F3A Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- 54AC
- Package/Case:
- 16-CDIP (0.300", 7.62mm)
- Packaging:
- Tube
- Product Status:
- Active
- Type:
- Data Selector/Multiplexer
- Circuit:
- 2 x 4:1
- Independent Circuits:
- 1
- Current - Output High, Low:
- 24mA, 24mA
- Voltage Supply Source:
- Single Supply
- Voltage - Supply:
- 1.5V ~ 5.5V
- Operating Temperature:
- -55°C ~ 125°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Through Hole
- Supplier Device Package:
- 16-CDIP
CD54AC153F3A FAQ
1.How can I place an order for CD54AC153F3A through Aetrix?
Please submit a Request for Quotation (RFQ) for CD54AC153F3A on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for CD54AC153F3A reliable?
The price and inventory of CD54AC153F3A are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for CD54AC153F3A is usually 5 days.
3.What payment methods are accepted for CD54AC153F3A?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for CD54AC153F3A transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for CD54AC153F3A?
CD54AC153F3A orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your CD54AC153F3A order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for CD54AC153F3A?
For technical support, including CD54AC153F3A datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your CD54AC153F3A requirements.
6.How does Aetrix verify that CD54AC153F3A is sourced from the original manufacturer or authorized distributors?
All CD54AC153F3A products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that CD54AC153F3A meets industry standards.
7.What is the process for return or replacement of CD54AC153F3A?
All CD54AC153F3A units undergo pre-shipment inspection (PSI). If there is an issue with CD54AC153F3A, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The CD54AC153F3A part is unused and in its original packaging.
Return procedure for CD54AC153F3A:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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