Texas Instruments CD54ACT138F3A
- Part No.:
- CD54ACT138F3A
- Manufacturer:
- Texas Instruments
- Category:
- Signal Switches, Multiplexers, Decoders
- Package:
- 16-CDIP (0.300", 7.62mm)
- Datasheet:
-
CD54ACT138F3A.pdf
- Description:
- 3-LINE TO 8-LINE INVERTING DECOD
- Quantity:
- Payment:

- Shipping:

Inventory:2,352
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
CD54ACT138F3A from Texas Instruments is a high-speed 3-line-to-8-line decoder/demultiplexer in a 16-pin CDIP (J) package, operating over –55°C to +125°C with 5V supply, ±24mA output drive, and propagation delays as low as 2.6ns (G2A/G2B → Y). It serves as a memory address decoder in military-grade embedded control systems requiring latchup immunity and MIL-STD-883 compliance.
For engineers reviewing the CD54ACT138F3A datasheet, CD54ACT138F3A pinout, CD54ACT138F3A application, or CD54ACT138F3A equivalent, this page delivers verified electrical specs, functional mode truth table, thermal metrics for harsh-environment PCB layout, and direct alternatives for radiation-tolerant system redesigns.
Technical Context
The CD54ACT138F3A implements positive-logic decoding with three enable inputs-two active-low (G2A, G2B) and one active-high (G1)-enabling cascaded 24-line or 32-line decoding without external inverters. Its TTL-compatible inputs interface directly with legacy bipolar logic while maintaining CMOS power efficiency.
Propagation delays are balanced across all input-to-output paths (tPLH/tPHL ≤ 12ns at –55°C to +125°C), and output drive supports fanout to 15 F-series devices. The device uses SCR-latchup-resistant CMOS process and exceeds 2kV HBM ESD per MIL-STD-883 Method 3015.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage | 4.5 V to 5.5 V - Ensures compatibility with standard 5V TTL/CMOS systems and stable operation under rail variation. |
| Operating Temperature | –55°C to +125°C - Qualified for military/aerospace applications per MIL-PRF-38535 Class B. |
| Output Drive | ±24 mA - Sustains robust signal integrity driving transmission lines or multiple gate loads without buffering. |
| Propagation Delay | 2.6 ns (min, G2A/G2B → Y) - Enables sub-10ns system-level address decode timing in high-speed memory subsystems. |
| Input Compatibility | TTL-voltage compatible (VIH = 2 V, VIL = 0.8 V) - Directly interfaces with 74LS, 74F, and other bipolar logic families. |
| ESD Rating | ±2000 V HBM - Meets MIL-STD-883 requirement for handling in uncontrolled environments. |
| Power Dissipation Cap | 110 pF typical Cpd - Predictable dynamic power consumption for thermal modeling in sealed enclosures. |
Pinout & Package
CD54ACT138F3A is housed in a 16-pin Ceramic Dual In-line Package (CDIP, J package), 19.3 mm × 9.4 mm body size, with through-hole mounting and SNPB (tin-lead) finish. The package is hermetically sealed and rated for extended temperature operation.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A, B, C | Binary select inputs | 3-bit address lines determining which of eight outputs (Y0–Y7) is asserted low; active-high logic. |
| G1 | Active-high enable | Primary enable: device active only when G1 = HIGH; enables hierarchical decoding with upstream logic. |
| G2A, G2B | Active-low strobe inputs | Secondary enables: both must be LOW for output activation; simplifies multi-chip address expansion. |
| Y0–Y7 | Active-low decoded outputs | One-hot low-active outputs; each corresponds to a unique A:B:C combination when enabled. |
| VCC | Positive supply | 5V nominal power rail; requires local 0.1 µF bypass capacitor per TI layout guidelines. |
| GND | Ground reference | Signal and power return; must be connected to low-impedance ground plane for noise immunity. |
Key Features
| Feature | Design Value |
|---|---|
| Three enable inputs (G1, G2A, G2B) | Enables 24-line decoding without external inverters and 32-line decoding with only one inverter - reduces board area and component count. |
| ±24 mA output drive | Drives 15 F-series logic loads directly - eliminates need for buffer stages in memory-enable paths. |
| SCR-latchup-resistant process | Guarantees immunity to destructive latchup under transient overvoltage or ESD events - critical for mission-critical avionics. |
| Balanced tPLH/tPHL | Minimizes skew between rising/falling edges across all outputs - essential for synchronous bus timing in real-time controllers. |
| MIL-STD-883 qualified | Validated for mechanical shock, vibration, temperature cycling, and hermeticity - meets QML-38535 Class B requirements. |
Applications
| Avionics Data Bus Decoder | Rad-Hard Memory Subsystem |
|---|---|
Use Scenario: Decoding ARINC 429 or MIL-STD-1553 address fields in flight control computers. IC Role / Device Role / Timing Role: Address decoder selecting discrete memory banks or peripheral registers during instruction fetch cycles. Use Value: 2.6 ns min propagation delay ensures decode completion within tight CPU wait-state windows. |
Use Scenario: Enabling radiation-tolerant SRAM modules in satellite on-board computers. IC Role / Device Role / Timing Role: High-reliability enable distributor routing chip-select signals to multiple memory ICs. Use Value: SCR-latchup resistance and –55°C to +125°C operation prevent single-event functional interrupts in LEO orbit. |
| Secure Crypto Module Selector | Tactical Radio Channel Router |
Use Scenario: Selecting between AES-256, SHA-2, and RSA accelerator blocks in encrypted comms hardware. IC Role / Device Role / Timing Role: Demultiplexer steering data streams to dedicated cryptographic engines based on command opcode. Use Value: TTL-compatible inputs accept direct connection to FPGA I/O banks without level-shifting. |
Use Scenario: Routing IF signals among multiple RF synthesizer channels in software-defined radios. IC Role / Device Role / Timing Role: Control-path decoder enabling specific frequency synthesis chains during channel hop sequences. Use Value: 2kV HBM ESD rating protects against static discharge in field-deployed handheld units. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 3-to-8 decoder applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| CD74ACT138E | Same logic function and AC/DC specs, but PDIP package (N), commercial temp range (–40°C to +85°C), RoHS-compliant NiPdAu finish. | Not qualified for military temperature extremes or MIL-STD-883 testing; suitable for industrial control, not avionics. | Select CD74ACT138E only for cost-sensitive non-military designs where extended temperature and hermetic sealing are unnecessary. |
| SN74ACT138N | Identical pinout and logic, but plastic DIP (N) package, commercial temp range, and no MIL-STD-883 qualification. | Lacks radiation tolerance and high-temp reliability; used in test equipment and lab prototypes. | Choose SN74ACT138N for bench validation or non-flight hardware where procurement lead time and cost outweigh environmental rigor. |
Compared with CD74ACT138E and SN74ACT138N, the CD54ACT138F3A uniquely provides hermetic CDIP packaging, full military temperature range, and MIL-PRF-38535 Class B certification - making it the sole option for deployed defense electronics requiring guaranteed long-term reliability under thermal cycling and mechanical stress.
Availability
CD54ACT138F3A is available at Aetrix Electronics and suitable for avionics data bus decoding, rad-hard memory subsystems, secure crypto module selection, and tactical radio channel routing requiring stable component supply across extended lifecycle programs.
Supply support for CD54ACT138F3A includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader delivering analog, embedded processing, and high-reliability logic solutions with over 50 years of aerospace and defense component heritage.
The CD54ACT138F3A belongs to TI's military-grade ACT logic family, engineered specifically for high-speed, low-power decoding in safety-critical systems where latchup immunity, ESD robustness, and extended temperature operation are mandatory.
FAQ
What is the maximum operating temperature of the CD54ACT138F3A?
The CD54ACT138F3A is rated for continuous operation from –55°C to +125°C ambient temperature, meeting MIL-PRF-38535 Class B requirements. This specification is validated per Test Method 1010 in MIL-STD-883 and applies to the CDIP (J) package with SNPB finish. Derating is not required within this range, and thermal resistance (RθJA) is not specified for CDIP due to its hermetic construction.
Does the CD54ACT138F3A support TTL-level input signals?
Yes, the CD54ACT138F3A features TTL-voltage compatible inputs: VIH = 2.0 V (min) and VIL = 0.8 V (max) at VCC = 5 V. This allows direct interfacing with legacy 74LS, 74F, and other bipolar logic families without level-shifting circuitry - a key design advantage confirmed in Section 4.3 of the SCHS329C datasheet.
How many enable inputs does the CD54ACT138F3A have, and what are their logic polarities?
The CD54ACT138F3A has three enable inputs: G1 (active-high), G2A (active-low), and G2B (active-low). All three must be simultaneously asserted (G1 = HIGH, G2A = LOW, G2B = LOW) for any output Y0–Y7 to respond to A/B/C inputs. This configuration is explicitly defined in Table 6-1 (Function Table) of the CD54ACT138F3A datasheet.
Is the CD54ACT138F3A pin-compatible with the CD74ACT138 series?
Yes, the CD54ACT138F3A shares identical pinout and logic functionality with CD74ACT138 variants in the same package type (e.g., CD74ACT138E in PDIP). However, CD54ACT138F3A uses a ceramic CDIP (J) package with different mechanical dimensions and solder finish (SNPB), so PCB footprints are not interchangeable despite functional equivalence.
What is the output drive capability of the CD54ACT138F3A?
The CD54ACT138F3A provides ±24 mA output drive current (IOL = 24 mA, IOH = –24 mA) at VCC = 4.5 V, enabling fanout to 15 F-series logic devices. This value is measured under recommended operating conditions and is specified in Section 1 (Features) and Table 4-5 (Electrical Characteristics) of the official TI datasheet SCHS329C.
CD54ACT138F3A Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- 54ACT
- Package/Case:
- 16-CDIP (0.300", 7.62mm)
- Packaging:
- Tube
- Product Status:
- Active
- Type:
- Decoder/Demultiplexer
- Circuit:
- 1 x 3:8
- Independent Circuits:
- 1
- Current - Output High, Low:
- 24mA, 24mA
- Voltage Supply Source:
- Single Supply
- Voltage - Supply:
- 4.5V ~ 5.5V
- Operating Temperature:
- -55°C ~ 125°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Through Hole
- Supplier Device Package:
- 16-CDIP
CD54ACT138F3A FAQ
1.How can I place an order for CD54ACT138F3A through Aetrix?
Please submit a Request for Quotation (RFQ) for CD54ACT138F3A on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for CD54ACT138F3A reliable?
The price and inventory of CD54ACT138F3A are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for CD54ACT138F3A is usually 5 days.
3.What payment methods are accepted for CD54ACT138F3A?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for CD54ACT138F3A transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for CD54ACT138F3A?
CD54ACT138F3A orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your CD54ACT138F3A order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for CD54ACT138F3A?
For technical support, including CD54ACT138F3A datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your CD54ACT138F3A requirements.
6.How does Aetrix verify that CD54ACT138F3A is sourced from the original manufacturer or authorized distributors?
All CD54ACT138F3A products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that CD54ACT138F3A meets industry standards.
7.What is the process for return or replacement of CD54ACT138F3A?
All CD54ACT138F3A units undergo pre-shipment inspection (PSI). If there is an issue with CD54ACT138F3A, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The CD54ACT138F3A part is unused and in its original packaging.
Return procedure for CD54ACT138F3A:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
CD54ACT138F3A Tags
-
SN74HC138DR
Texas Instruments

-
TC7SB3157CFU,LF(CT
Toshiba Semiconductor and Storage

-
74CBTLV3257PW,118
Nexperia USA Inc.
-
SN74CBTLV3257PWR
Texas Instruments

-
74CBTLV3257GUX
Nexperia USA Inc.

-
74HC154BQ,118
Nexperia USA Inc.

-
P3S0200GMX
NXP USA Inc.

-
SN74CB3Q3245PWR
Texas Instruments
-
SN74CB3Q3257RGYR
Texas Instruments

-
TCA9543APWR
Texas Instruments
-
TCA9546APWR
Texas Instruments

-
SN74HC138N
Texas Instruments
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

