Texas Instruments CD74AC112M96G4

Overview

CD74AC112M96G4 from Texas Instruments is a dual J-K negative-edge-triggered flip-flop with independent preset and clear inputs, operating across 1.5 V to 5.5 V supply range, delivering ±24 mA output drive, 100 MHz max clock frequency at 5 V, and 2.6 ns typical tPHL propagation delay - used in synchronous logic control, state machine sequencing, and digital counter design.

For engineers reviewing the CD74AC112M96G4 datasheet, CD74AC112M96G4 pinout, CD74AC112M96G4 application, or CD74AC112M96G4 equivalent, this page delivers verified functional identity, SOIC-16 package mapping, timing behavior at multiple VCC levels, noise-immune CMOS operation, and direct alternatives for logic-level-compatible J-K flip-flop replacement.

Technical Context

The CD74AC112M96G4 implements two fully independent J-K flip-flops sharing no internal coupling, each triggered exclusively on the negative-going edge of CLK. Preset (PRE) and Clear (CLR) are asynchronous active-low inputs that override clocked operation, enabling immediate state initialization or reset without clock dependency.

Its AC-series CMOS process ensures balanced high/low propagation delays (tPLH ≈ tPHL), rail-to-rail output swing, and SCR-latchup resistance. Timing parameters-including setup time (4 ns min at 5 V), hold time (0 ns), and recovery time (2.5 ns)-are specified across –55°C to 125°C, supporting military-grade and extended-temperature industrial use.

Key Specifications

Pinout & Package

CD74AC112M96G4 is housed in a 16-pin SOIC (D) package with 1.27 mm pitch, JEDEC MS-012 compliant, moisture sensitivity level 1 (260°C peak reflow), and tape-and-reel packaging (2500 units/reel).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual J-K flip-flop applications.

Compared with CD74AC112M96G4, SN74AC112DR sacrifices extended temperature range for lower unit cost, while CD74HC112M96 trades speed and drive for reduced quiescent current - making CD74AC112M96G4 optimal for high-reliability, wide-temperature, high-speed logic control where timing precision and robustness are non-negotiable.

Availability

CD74AC112M96G4 is available at Aetrix Electronics and suitable for industrial PLC sequencing, aerospace avionics state machines, and digital test equipment control requiring stable component supply across extended temperature ranges and long production lifecycles.

Supply support for CD74AC112M96G4 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader founded in 1930, specializing in analog, embedded processing, and logic solutions with broad industrial, automotive, and aerospace portfolio coverage.

The CD74AC112M96G4 belongs to TI's Advanced CMOS (AC) logic family, engineered for high-speed, low-power, wide-supply-voltage digital control in mission-critical systems demanding reliability across extreme environmental conditions.

FAQ

What is the maximum clock frequency supported by CD74AC112M96G4 at 3.3 V?

The CD74AC112M96G4 supports up to 81 MHz maximum clock frequency at VCC = 3.3 V over the –40°C to +85°C operating range, with 5.6 ns minimum setup time and 0 ns hold time required for reliable J/K data capture on the negative clock edge. This performance enables use in 3.3 V FPGA companion logic and high-speed interface glue logic.

Does CD74AC112M96G4 support 1.8 V operation?

Yes, CD74AC112M96G4 is fully specified down to 1.5 V supply voltage, including guaranteed functionality, timing, and noise immunity at 1.8 V. At 1.8 V, it achieves 9 MHz max clock frequency with 50 ns setup time, making it suitable for low-voltage portable and IoT edge-node control circuits.

Is CD74AC112M96G4 pin-compatible with CD74AC112M?

Yes, CD74AC112M96G4 and CD74AC112M share identical SOIC-16 (D) package dimensions, pin assignment, and marking (AC112M), with CD74AC112M96G4 being the tape-and-reel variant of the same device. Both comply with JEDEC MO-153 and have identical thermal and electrical specifications.

What is the meaning of "negative-edge-triggered" in CD74AC112M96G4?

"Negative-edge-triggered" means the CD74AC112M96G4 transfers data from J and K inputs to Q and Q outputs precisely at the falling transition (high-to-low) of the clock signal. This behavior is voltage-threshold-based-not dependent on fall time-and allows synchronization to system clocks with defined falling edges, reducing susceptibility to noise on rising edges.

How does the asynchronous clear function work in CD74AC112M96G4?

In CD74AC112M96G4, asserting CLR low forces the corresponding Q output low and Q high immediately-regardless of clock state or J/K input levels. This asynchronous action overrides all clocked behavior, enabling instant reset for safety-critical functions like emergency shutdown or power-on initialization without waiting for the next clock edge.