Texas Instruments CD74AC253M
- Part No.:
- CD74AC253M
- Manufacturer:
- Texas Instruments
- Category:
- Signal Switches, Multiplexers, Decoders
- Package:
- 16-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
CD74AC253M.pdf
- Description:
- IC MULTIPLEXER 2 X 4:1 16SOIC
- Quantity:
- Payment:

- Shipping:

Inventory:887
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
CD74AC253M from Texas Instruments is a dual 4-input three-state multiplexer in SOIC-16 package, featuring 1.5V–5.5V supply operation, ±24mA output drive, 6.3ns typical propagation delay at 5V/25°C/50pF, and SCR-latchup-resistant CMOS logic. It selects one of four inputs per section using common S0/S1 select lines and enables high-impedance outputs via independent 1OE/2OE controls - used in digital signal routing for industrial control I/O expansion.
For engineers reviewing the CD74AC253M datasheet, CD74AC253M pinout, CD74AC253M application, or CD74AC253M equivalent, key selection criteria include voltage-range flexibility (1.5–5.5V), balanced noise immunity at 30% of VCC, three-state bus-driving capability, and compatibility with FAST™-level timing while consuming significantly less power.
Technical Context
The CD74AC253M implements two independent 4:1 multiplexer sections sharing S0 and S1 select inputs, each with dedicated three-state output enable (1OE, 2OE). Its Advanced CMOS Logic architecture delivers TTL-compatible input thresholds across the full 1.5V–5.5V supply range and supports fanout to 15 FAST™ ICs or direct 50Ω transmission-line driving.
Propagation delays are balanced between select-to-output (tPLH/tPHL ≤20ns at 5V) and data-input-to-output paths (≤12.1ns at 5V), with output enable/disable delays as low as 10.5ns. Input and output capacitances are specified at 10pF and 15pF respectively, supporting high-speed digital interface design without external buffering.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage Range | 1.5V to 5.5V - enables interoperability across 1.8V, 3.3V, and 5V logic domains without level shifters |
| Propagation Delay (S0/S1 → Y) | 5.2ns typ / 20ns max at 5V - supports ≥50MHz switching in synchronous bus applications |
| Output Drive Current | ±24mA - drives 50Ω transmission lines directly or fans out to 15 FAST™ loads |
| Input Thresholds | VIL = 0.3V, VIH = 3.85V at 5.5V - provides 30% noise margin relative to VCC |
| Three-State Leakage | ±5µA max at -40°C to 85°C - ensures reliable bus isolation during disable states |
| ESD Protection | ≥2kV HBM - meets MIL-STD-883 Method 3015 for robust handling in manufacturing environments |
| Operating Temperature | -55°C to +125°C - qualified for extended industrial and automotive under-hood applications |
Pinout & Package
CD74AC253M is housed in a 16-pin Small Outline Integrated Circuit (SOIC) package with standard 1.27mm pitch and JEDEC MS-012AC outline. Pin 1 is located at the top-left corner with quadrants assigned per tape-and-reel specification Q1 orientation.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | 1OE (Output Enable, Section 1) | Active-HIGH control: asserts high-impedance state on 1Y when HIGH |
| 2 | S1 (Select Input, MSB) | Common select line for both sections; defines bit position in 4-input decode |
| 3 | 1I3 (Data Input, Section 1) | Most significant data input for Section 1; routed to 1Y when S1S0 = 11 |
| 4 | 1I2 (Data Input, Section 1) | Second most significant data input for Section 1; selected when S1S0 = 10 |
| 5 | 1I1 (Data Input, Section 1) | Second least significant data input for Section 1; selected when S1S0 = 01 |
| 6 | 1I0 (Data Input, Section 1) | Least significant data input for Section 1; selected when S1S0 = 00 |
| 7 | GND | Power ground reference for all internal logic and I/O circuits |
| 8 | 1Y (Output, Section 1) | Three-state output for Section 1; reflects selected input when 1OE = LOW |
| 9 | VCC | Positive supply rail; supports 1.5V–5.5V operation with stable regulation |
| 10 | S0 (Select Input, LSB) | Common select line for both sections; defines LSB in 2-bit select word |
| 11 | 2I3 (Data Input, Section 2) | Most significant data input for Section 2; routed to 2Y when S1S0 = 11 |
| 12 | 2I2 (Data Input, Section 2) | Second most significant data input for Section 2; selected when S1S0 = 10 |
| 13 | 2I1 (Data Input, Section 2) | Second least significant data input for Section 2; selected when S1S0 = 01 |
| 14 | 2I0 (Data Input, Section 2) | Least significant data input for Section 2; selected when S1S0 = 00 |
| 15 | 2Y (Output, Section 2) | Three-state output for Section 2; reflects selected input when 2OE = LOW |
| 16 | 2OE (Output Enable, Section 2) | Active-HIGH control: asserts high-impedance state on 2Y when HIGH |
Key Features
| Feature | Design Value |
|---|---|
| Buffered Inputs | Reduces capacitive loading on upstream drivers and improves signal integrity across PCB traces |
| Balanced Propagation Delays | Minimizes skew between select and data paths, enabling deterministic timing in synchronous multiplexing |
| SCR-Latchup-Resistant Process | Prevents destructive latch-up events under transient overvoltage or ESD stress conditions |
| 1.5V–5.5V Wide-Voltage Operation | Eliminates need for separate voltage translators in mixed-supply systems such as FPGA I/O banks |
| ±24mA Output Drive | Supports direct connection to terminated transmission lines or legacy TTL/CMOS loads without buffers |
Applications
| Industrial PLC I/O Expansion | FPGA Configuration Multiplexing |
|---|---|
Use Scenario: Routing multiple sensor analog-to-digital converter outputs to a shared microcontroller ADC channel in programmable logic controllers. IC Role / Device Role / Timing Role: Dual 4:1 multiplexer providing time-shared access to eight discrete analog channels via two independent select buses. Use Value: Enables cost-effective consolidation of eight sensor inputs onto one ADC port while maintaining <20ns channel-switching latency. | Use Scenario: Selecting among multiple configuration bitstreams stored in parallel flash memory for FPGA partial reconfiguration. IC Role / Device Role / Timing Role: Bus-select switch that routes address/data lines from flash to FPGA configuration pins based on mode register settings. Use Value: Allows dynamic FPGA functional reassignment without external CPLD or dedicated configuration controller hardware. |
| Test Equipment Signal Routing | Automotive Body Control Module |
Use Scenario: Switching calibration reference voltages into precision DACs during automated test equipment self-calibration sequences. IC Role / Device Role / Timing Role: Precision analog signal selector with low leakage (<5µA) and matched propagation delays across channels. Use Value: Ensures measurement repeatability by eliminating path-dependent offset drift during multi-point calibration sweeps. | Use Scenario: Consolidating door lock actuator, window motor, and mirror control signals onto shared CAN transceiver diagnostic lines. IC Role / Device Role / Timing Role: Digital signal combiner enabling bidirectional communication between microcontroller GPIOs and shared diagnostic bus. Use Value: Reduces BOM count and PCB layer count in space-constrained body electronics modules operating at -40°C to +125°C. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual 4-input multiplexer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74AC253N | PDIP-16 package only; identical AC-series electrical specs and pinout | Limited to through-hole assembly; lacks SOIC thermal and density advantages | Select when legacy through-hole prototyping or repair is required |
| CD74ACT253M | TTL-compatible input thresholds (VIH=2V min); 4.5–5.5V supply only; otherwise identical SOIC-16 footprint | Requires strict 5V supply; not suitable for 3.3V or mixed-voltage systems | Select only for pure 5V designs needing TTL-level compatibility |
Compared with SN74AC253N and CD74ACT253M, the CD74AC253M uniquely supports 1.5–5.5V operation in SOIC-16, offering broader voltage interoperability and surface-mount manufacturability without sacrificing speed or drive strength.
Availability
CD74AC253M is available at Aetrix Electronics and suitable for industrial automation, test instrumentation, and automotive body electronics requiring stable component supply across extended temperature ranges and mixed-voltage logic interfaces.
Supply support for CD74AC253M includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and logic solutions with over 90 years of innovation in high-reliability components.
The CD74AC253M belongs to TI's Advanced CMOS (AC) logic family, designed for high-speed, low-power digital signal routing in mixed-supply industrial and automotive systems where voltage flexibility and noise immunity are critical.
FAQ
What is the maximum operating supply voltage for CD74AC253M?
The CD74AC253M supports a maximum DC supply voltage of 6V, but its recommended operational range is 1.5V to 5.5V per the datasheet's Operating Conditions table. Exceeding 5.5V may cause excessive current draw or reliability degradation, even though absolute maximum rating allows up to 6V. Always operate CD74AC253M within 1.5–5.5V for guaranteed functionality and lifetime performance.
Does CD74AC253M support 3.3V logic levels?
Yes, CD74AC253M fully supports 3.3V operation: input thresholds scale with VCC (VIH = 2.1V min, VIL = 0.9V max at 3V), and output drive remains ±24mA. At 3.3V, propagation delay is 4.7ns typical, and noise immunity is maintained at 30% of supply - making CD74AC253M ideal for interfacing with 3.3V FPGAs, microcontrollers, and peripheral ICs.
Can CD74AC253M replace CD74ACT253M in an existing design?
CD74AC253M can replace CD74ACT253M only if the system operates at 3.3V or lower and does not require strict TTL-compatible input thresholds. CD74ACT253M mandates 4.5–5.5V and has VIH ≥2V, whereas CD74AC253M works from 1.5V and has VIH = 0.7×VCC. Verify input drive compatibility before substitution; CD74AC253M is not a drop-in replacement in pure 5V TTL systems.
What is the thermal resistance θJA for CD74AC253M in SOIC package?
The datasheet does not specify θJA for the SOIC package of CD74AC253M - it lists "___" in the Thermal Information table. However, TI's generic SOIC-16 (D package) θJA is typically 130°C/W on a 2-layer board with 1 in² copper pour. For precise thermal modeling, refer to TI's SOIC-16 thermal characterization reports or use measured junction-to-ambient data under your specific PCB layout and airflow conditions.
Is CD74AC253M pin-compatible with SN74LS253?
No, CD74AC253M is not pin-compatible with SN74LS253. While both are dual 4-input multiplexers with three-state outputs, SN74LS253 uses different pin assignments: its OE inputs are active-low (1G, 2G), and outputs are labeled Y1/Y2 instead of 1Y/2Y. The CD74AC253M has active-high OE (1OE/2OE) and follows TI's AC/ACT pinout convention - direct replacement requires PCB redesign.
CD74AC253M Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- 74AC
- Package/Case:
- 16-SOIC (0.154", 3.90mm Width)
- Packaging:
- Bulk
- Product Status:
- Obsolete
- Type:
- Multiplexer
- Circuit:
- 2 x 4:1
- Independent Circuits:
- 1
- Current - Output High, Low:
- 75mA, 75mA
- Voltage Supply Source:
- Single Supply
- Voltage - Supply:
- 1.5V ~ 5.5V
- Operating Temperature:
- -55°C ~ 125°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-SOIC
CD74AC253M FAQ
1.How can I place an order for CD74AC253M through Aetrix?
Please submit a Request for Quotation (RFQ) for CD74AC253M on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for CD74AC253M reliable?
The price and inventory of CD74AC253M are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for CD74AC253M is usually 5 days.
3.What payment methods are accepted for CD74AC253M?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for CD74AC253M transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for CD74AC253M?
CD74AC253M orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your CD74AC253M order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for CD74AC253M?
For technical support, including CD74AC253M datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your CD74AC253M requirements.
6.How does Aetrix verify that CD74AC253M is sourced from the original manufacturer or authorized distributors?
All CD74AC253M products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that CD74AC253M meets industry standards.
7.What is the process for return or replacement of CD74AC253M?
All CD74AC253M units undergo pre-shipment inspection (PSI). If there is an issue with CD74AC253M, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The CD74AC253M part is unused and in its original packaging.
Return procedure for CD74AC253M:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
CD74AC253M Tags
-
SN74HC138DR
Texas Instruments

-
TC7SB3157CFU,LF(CT
Toshiba Semiconductor and Storage

-
74CBTLV3257PW,118
Nexperia USA Inc.
-
SN74CBTLV3257PWR
Texas Instruments

-
74CBTLV3257GUX
Nexperia USA Inc.

-
74HC154BQ,118
Nexperia USA Inc.

-
P3S0200GMX
NXP USA Inc.

-
SN74CB3Q3245PWR
Texas Instruments
-
SN74CB3Q3257RGYR
Texas Instruments

-
TCA9543APWR
Texas Instruments
-
TCA9546APWR
Texas Instruments

-
SN74HC138N
Texas Instruments
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
