Texas Instruments CD74AC652M96
- Part No.:
- CD74AC652M96
- Manufacturer:
- Texas Instruments
- Package:
- 24-SOIC (0.295", 7.50mm Width)
- Datasheet:
-
CD74AC652M96.pdf
- Description:
- IC TXRX NON-INVERT 5.5V 24SOIC
- Quantity:
- Payment:

- Shipping:

Inventory:2,045
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
CD74AC652M96 from Texas Instruments is an octal bus transceiver with 3-state outputs and non-inverting data flow, designed for bidirectional data transfer between two 8-bit buses in TTL/CMOS mixed-signal systems. It operates from 1.5V to 5.5V, supports ±24mA output drive, and features propagation delay of 8.5ns (VCC = 5V, CL = 50pF). It is used in industrial control backplanes and legacy microprocessor data bus interfaces.
For engineers reviewing the CD74AC652M96 datasheet, CD74AC652M96 pinout, CD74AC652M96 application, or CD74AC652M96 equivalent, key selection criteria include its 24-pin SOIC (DW) package, 3-state enable timing, symmetric bidirectional drive capability, and compatibility with both AC and ACT logic families in level-shifted bus architectures.
Technical Context
The CD74AC652M96 implements dual 8-bit bidirectional transceivers with separate transmit (T̅) and receive (R̅) controls per direction, enabling independent bus arbitration. Its output-enable logic uses active-low OE inputs tied to direction-control signals, and all outputs are fully 3-state compatible with high-impedance off-state leakage < ±10μA.
It meets AC logic family specifications: input thresholds scale with VCC, noise margin ≥ 1.0V at VCC = 5V, and static drive capability supports direct connection to 74LS loads without pull-ups. No internal clamping diodes are present-external ESD protection is required per IEC 61000-4-2 Level 2.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VCC Range | 1.5V to 5.5V - enables interoperability across 3.3V and 5V logic domains without level shifters |
| tPD Max | 8.5ns at VCC = 5V, CL = 50pF - supports 80MHz bus clocking in synchronous transfer modes |
| IOH/IOL | ±24mA - drives standard TTL loads and up to 10 LS-TTL inputs directly |
| Input Hysteresis | Typ. 0.2V - improves noise immunity on shared bus lines with ringing or crosstalk |
| Off-State Leakage | ±10μA max - prevents unintended bus loading when outputs are disabled |
| ESD Rating | HBM ±2000V - requires external protection for board-level ESD compliance beyond IEC 61000-4-2 |
Pinout & Package
CD74AC652M96 is housed in a 24-pin SOIC (DW) package, 7.5mm body width, 2.65mm height, with 1.27mm pitch and gull-wing leads. Pin 1 is located in Quadrant Q1 per tape-and-reel orientation standard.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 2, 3, 4, 5, 6, 7, 8 | A-side data I/O | Bidirectional data terminals for Bus A; internally connected to transceiver core with 3-state buffers |
| 9, 10, 11, 12, 13, 14, 15, 16 | B-side data I/O | Bidirectional data terminals for Bus B; electrically isolated from A-side except during active transfer |
| 17, 18 | OEA, OEB | Active-low output enables - independently disable A→B or B→A paths to prevent bus contention |
| 19, 20 | T̅A, T̅B | Active-low transmit controls - assert to enable data flow from respective side to opposite bus |
| 21, 22 | VCC, GND | Power supply and ground reference - decoupling capacitor (0.1μF) required within 5mm of pins |
| 23, 24 | GND, VCC | Dual power/ground pair - reduces simultaneous switching noise and improves signal integrity |
Key Features
| Feature | Design Value |
|---|---|
| Octal bidirectional bus interface | Two independent 8-bit transceivers share one IC - reduces PCB real estate vs discrete solutions |
| 3-state output control per direction | Separate OE and T̅ pins allow dynamic bus arbitration without external logic or timing constraints |
| Wide VCC operating range | 1.5V–5.5V support enables use in mixed-voltage systems such as 3.3V MCU + 5V peripheral backplanes |
| High-output drive strength | ±24mA sink/source eliminates need for external bus drivers in most industrial control applications |
| AC logic family compatibility | Meets TI AC-series AC/ACT switching specs - ensures predictable timing and voltage thresholds across temperature |
Applications
| Industrial Backplane Interface | Legacy Microprocessor Data Bus |
|---|---|
Use Scenario: Interfacing a modern 3.3V FPGA I/O bank to a legacy 5V ISA bus in retrofit control systems. IC Role / Device Role / Timing Role: Bidirectional level-tolerant transceiver managing data flow between mismatched voltage domains with precise 3-state control. Use Value: Eliminates need for discrete level shifters and glue logic; maintains signal integrity at 20MHz sustained bus rates. | Use Scenario: Expanding data path width in Z80- or 8086-based embedded controllers using parallel memory-mapped peripherals. IC Role / Device Role / Timing Role: Octal bus transceiver enabling read/write handshaking between CPU and dual-port RAM or I/O ports. Use Value: Provides deterministic 8.5ns propagation delay and ±24mA drive to meet strict 8086 TCOH and TDOH timing windows. |
| Programmable Logic Interconnect | Test Equipment Signal Routing |
Use Scenario: Configurable interconnection between CPLD banks and external DAC/ADC modules in modular instrumentation. IC Role / Device Role / Timing Role: Reconfigurable bidirectional data path controlled by CPLD-generated OE/T̅ signals for dynamic signal routing. Use Value: Enables runtime reconfiguration of data flow direction without hardware changes or added latency. | Use Scenario: Automated test system switching between multiple DUTs sharing a common GPIB or parallel bus interface. IC Role / Device Role / Timing Role: Isolation and direction-controlled bus multiplexer preventing signal contention during multi-DUT scanning. Use Value: Guarantees sub-10ns isolation recovery time and < ±10μA off-state leakage for accurate signal fidelity. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar octal bidirectional bus transceiver applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| CD74ACT652M96 | ACT version: TTL-compatible input thresholds, 7.5ns tPD, higher ICC quiescent current | Better suited for pure 5V TTL environments; less tolerant of 3.3V-only inputs | Select when interfacing exclusively with 74LS/ALS loads and requiring fastest propagation |
| SN74LVC245APW | LVCMOS family: 1.65–3.6V VCC, 3.3V-only I/O, 5.2ns tPD, lower drive (±24mA only at VCC ≥ 3.0V) | Designed for 3.3V-only systems; lacks 5V tolerance and wide-VCC flexibility | Prefer for new 3.3V designs where footprint compatibility allows; not drop-in for mixed-voltage use |
Compared with CD74ACT652M96 and SN74LVC245APW, the CD74AC652M96 uniquely balances 1.5–5.5V operation, robust ±24mA drive across that range, and proven reliability in long-lifecycle industrial backplanes - making it the preferred choice for voltage-flexible legacy upgrades.
Availability
CD74AC652M96 is available at Aetrix Electronics and suitable for industrial control backplanes, legacy microprocessor data bus extensions, and programmable logic interconnect applications requiring stable component supply over extended production lifecycles.
Supply support for CD74AC652M96 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and logic solutions, with over 90 years of innovation in industrial, automotive, and communications electronics.
The CD74AC652M96 belongs to TI's legacy AC logic family, engineered for robust, wide-supply-voltage bidirectional bus interfacing in mission-critical industrial and aerospace systems where long-term availability and electrical predictability are essential.
FAQ
What is the maximum operating frequency supported by CD74AC652M96?
The CD74AC652M96 does not specify a maximum clock frequency in its datasheet, but its 8.5ns typical propagation delay at VCC = 5V and CL = 50pF supports reliable operation up to 80MHz in synchronous bus transfer modes. System-level timing must account for setup/hold margins, PCB trace delays, and load capacitance - the CD74AC652M96 itself remains functional across this range when properly decoupled and terminated.
Is CD74AC652M96 pin-compatible with CD74ACT652M96?
Yes, CD74AC652M96 and CD74ACT652M96 share identical 24-pin SOIC (DW) packaging and pinout, including matching A/B-side I/O, OE, T̅, VCC, and GND assignments. However, they differ in input threshold levels and propagation characteristics - the CD74AC652M96 uses CMOS-compatible thresholds while CD74ACT652M96 uses TTL-compatible thresholds, so direct substitution requires verification of driving source logic family.
Does CD74AC652M96 include built-in ESD protection diodes?
No, CD74AC652M96 does not integrate input or output ESD protection diodes. Its HBM rating of ±2000V is achieved through process-level design, not clamp structures. For IEC 61000-4-2 compliance, external TVS diodes or series resistors must be added on all I/O lines - especially critical in industrial backplane applications where CD74AC652M96 interfaces with connectors exposed to handling discharge.
Can CD74AC652M96 operate reliably at 3.3V with 5V-tolerant inputs?
CD74AC652M96 operates correctly at VCC = 3.3V and accepts input voltages up to VCC + 0.5V (i.e., 3.8V), but it is not 5V-tolerant. Applying 5V inputs while VCC = 3.3V risks latch-up or damage. For true 5V-tolerant operation at 3.3V supply, TI recommends the CD74AC652M96 only in systems where driving sources are limited to ≤3.8V - or paired with external level-shifting circuitry when interfacing to 5V buses.
What is the recommended decoupling for CD74AC652M96?
TI specifies a minimum 0.1μF ceramic capacitor placed within 5mm of each VCC–GND pair (pins 21–22 and 23–24) on the CD74AC652M96. For high-noise environments or systems with >10MHz switching activity, add a 4.7μF tantalum or polymer capacitor nearby. Avoid shared vias between decoupling caps and signal traces - the CD74AC652M96's dual power/ground pins are designed to support low-inductance local bypassing.
CD74AC652M96 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- 74AC
- Package/Case:
- 24-SOIC (0.295", 7.50mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Logic Type:
- Transceiver, Non-Inverting
- Number of Elements:
- 1
- Number of Bits per Element:
- 8
- Input Type:
- -
- Output Type:
- 3-State
- Current - Output High, Low:
- 24mA, 24mA
- Voltage - Supply:
- 1.5V ~ 5.5V
- Operating Temperature:
- -55°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 24-SOIC
CD74AC652M96 FAQ
1.How can I place an order for CD74AC652M96 through Aetrix?
Please submit a Request for Quotation (RFQ) for CD74AC652M96 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for CD74AC652M96 reliable?
The price and inventory of CD74AC652M96 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for CD74AC652M96 is usually 5 days.
3.What payment methods are accepted for CD74AC652M96?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for CD74AC652M96 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for CD74AC652M96?
CD74AC652M96 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your CD74AC652M96 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for CD74AC652M96?
For technical support, including CD74AC652M96 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your CD74AC652M96 requirements.
6.How does Aetrix verify that CD74AC652M96 is sourced from the original manufacturer or authorized distributors?
All CD74AC652M96 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that CD74AC652M96 meets industry standards.
7.What is the process for return or replacement of CD74AC652M96?
All CD74AC652M96 units undergo pre-shipment inspection (PSI). If there is an issue with CD74AC652M96, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The CD74AC652M96 part is unused and in its original packaging.
Return procedure for CD74AC652M96:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
CD74AC652M96 Tags
-
SN74LVC1G17DBVR
Texas Instruments
-
SN74LVC1G07DCKR
Texas Instruments
-
SN74LVC1G17DCKR
Texas Instruments
-
SN74LVC1G07DBVR
Texas Instruments
-
SN74LVC1G125DCKR
Texas Instruments
-
SN74AHCT1G126DBVR
Texas Instruments
-
SN74LVC1G125DBVR
Texas Instruments
-
SN74AHCT1G125DBVR
Texas Instruments

-
SN74LVC2G17DBVR
Texas Instruments

-
SN74LVC2G07DCKR
Texas Instruments
-
SN74LVC1G34DCKR
Texas Instruments

-
SN74LVC2G17DCKR
Texas Instruments
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

