Texas Instruments CD74ACT273PW
- Part No.:
- CD74ACT273PW
- Manufacturer:
- Texas Instruments
- Category:
- Flip Flops
- Package:
- 20-TSSOP (0.173", 4.40mm Width)
- Datasheet:
-
CD74ACT273PW.pdf
- Description:
- IC FF D-TYPE SNGL 8BIT 20TSSOP
- Quantity:
- Payment:

- Shipping:

Inventory:4,158
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
CD74ACT273PW from Texas Instruments is an octal D-type flip-flop with asynchronous master reset, implemented in advanced CMOS technology. It features 8-bit edge-triggered storage, ±24mA output drive, 6.5ns typical propagation delay at 5V/25°C, and operates across –55°C to +125°C. It serves as a synchronous data latch in digital control logic, bus interface buffering, and state register banks.
For engineers reviewing the CD74ACT273PW datasheet, CD74ACT273PW pinout, CD74ACT273PW application, or CD74ACT273PW equivalent, key selection criteria include its 5V-only ACT-series voltage range (4.5–5.5V), TSSOP-20 package footprint, TTL-compatible input thresholds, and guaranteed 97MHz maximum clock frequency at 25°C.
Technical Context
The CD74ACT273PW implements eight independent D flip-flops sharing a common rising-edge-triggered clock (CP) and active-low asynchronous master reset (!MR). All outputs update synchronously on the positive-going CP edge, while !MR forces Qn = L independently of CP timing.
It uses ACT-series silicon with TTL-compatible input thresholds (VIH = 2.0V min, VIL = 0.8V max at VCC = 4.5–5.5V), balanced propagation delays (tPLH/tPHL ≤ 13.5ns max over full temperature range), and SCR-latchup-resistant design for robust operation in noisy industrial environments.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Logic Family | ACT (Advanced CMOS TTL-compatible) |
| Supply Voltage Range | 4.5V to 5.5V - mandates dedicated 5V rail; not 3.3V compatible |
| Max Clock Frequency | 97MHz at 25°C - supports high-speed control loop sampling and data capture |
| Propagation Delay | 3.5ns (min) to 13.5ns (max) - enables precise timing alignment in synchronous systems |
| Output Drive | ±24mA per pin - directly drives 50Ω transmission lines or 15 FAST™ ICs without buffers |
| Operating Temperature | –55°C to +125°C - qualified for extended industrial and automotive under-hood applications |
| Input Thresholds | VIH ≥ 2.0V, VIL ≤ 0.8V - ensures reliable interfacing with standard TTL and 5V CMOS logic |
Pinout & Package
TSSOP-20 package (5.00 mm × 6.4 mm body, 0.65 mm pitch), lead-free with NIPDAU finish, moisture sensitivity level 1 (260°C reflow).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 !MR | Asynchronous master reset input | Active-low; forces all Qn = L regardless of CP state - critical for power-on initialization and fault recovery |
| 2 Q0 – 9 Q3, 12 Q4 – 19 Q7 | Registered data outputs | Eight buffered complementary outputs; fanout-capable with controlled edge rates |
| 3–4, 7–8, 13–14, 17–18 D0–D7 | Data inputs | Individual D-type latch inputs; each sampled on CP rising edge |
| 10 GND | Ground reference | Primary return path for logic and output currents; requires low-inductance PCB connection |
| 11 CP | Clock input | Rising-edge triggered; minimum pulse width 5.3ns - defines minimum clock period and setup/hold timing budget |
| 20 VCC | Power supply | 5V nominal supply; requires local 0.1µF bypass capacitor per VCC pin to suppress switching noise |
Key Features
| Feature | Design Value |
|---|---|
| SCR-latchup-resistant process | Guarantees immunity to destructive latchup under transient overvoltage or ESD stress in harsh environments |
| ±24mA output drive | Eliminates need for external line drivers when interfacing with 50Ω backplanes or long PCB traces |
| 6.5ns typical tPD at 5V | Enables sub-10ns timing margins in high-speed control registers and pipeline stages |
| TTL-compatible input thresholds | Ensures seamless interoperability with legacy 5V microcontrollers, FPGAs, and peripheral ICs without level shifters |
| –55°C to +125°C operation | Supports deployment in uncontrolled ambient environments including motor control enclosures and outdoor infrastructure |
Applications
| Industrial PLC I/O Expansion | Digital Power Supply Sequencing |
|---|---|
Use Scenario: Expanding discrete input/output points in programmable logic controllers using parallel bus interfaces. IC Role / Device Role / Timing Role: Octal latch holding command states from CPU bus; synchronized to system clock for deterministic update timing. Use Value: Provides galvanically isolated, noise-immune state retention with guaranteed 125°C operation in cabinet-mounted controllers. | Use Scenario: Controlling enable signals for multiple DC-DC converter rails during cold-start and fault recovery sequences. IC Role / Device Role / Timing Role: Synchronized register bank storing power-up order and fault-mute states; updated only on validated clock edges. Use Value: Prevents race conditions between rail enables via strict edge-triggered update and hard reset capability. |
| Automotive Body Control Module | Test Equipment Pattern Generation |
Use Scenario: Managing headlight, wiper, and door lock actuator signals in centralized vehicle body electronics units. IC Role / Device Role / Timing Role: Output register latching MCU GPIO commands; reset pin tied to watchdog timeout for fail-safe deactivation. Use Value: Delivers AEC-Q100–compatible reliability and wide-temp operation required for under-dash mounting locations. | Use Scenario: Generating deterministic multi-bit stimulus patterns for IC functional testing on automated test equipment (ATE) platforms. IC Role / Device Role / Timing Role: Parallel pattern register feeding DUT input bus; clocked from precision ATE timing generator. Use Value: Enables sub-10ns pattern edge accuracy and glitch-free state transitions essential for high-speed digital validation. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar octal D flip-flop with reset applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74ACT273PWR | Identical electrical specs and pinout; same TSSOP-20 package; TI's current production variant of CD74ACT273PWR | No functional difference; fully interchangeable in new designs and replacements | Select SN74ACT273PWR for new designs requiring guaranteed long-term availability and TI's latest manufacturing release |
| CD74AC273PW | AC-series variant: wider 1.5–5.5V supply range but lower drive (±24mA not guaranteed), slower max speed (114MHz vs 97MHz at 5V), and reduced noise immunity | Suitable for mixed-voltage systems but lacks ACT's TTL compatibility and robust 5V drive | Choose CD74AC273PW only if dual-supply flexibility (e.g., 3.3V/5V coexistence) is required and 5V drive margin is non-critical |
Compared with CD74ACT273PW, SN74ACT273PWR offers identical performance with assured supply continuity, while CD74AC273PW trades 5V drive strength and TTL compatibility for broader voltage range - making the former ideal for stable 5V systems and the latter for multi-rail legacy integration.
Availability
CD74ACT273PW is available at Aetrix Electronics and suitable for industrial PLC I/O expansion, automotive body control modules, and digital power supply sequencing requiring stable component supply and extended temperature support.
Supply support for CD74ACT273PW includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and logic solutions with over 90 years of innovation in industrial, automotive, and communications markets.
The CD74ACT273PW belongs to TI's legacy high-speed logic portfolio designed for robust, pin-compatible replacements of bipolar TTL in industrial control, instrumentation, and automotive subsystems where reliability across extreme temperatures is mandatory.
FAQ
What is the recommended operating voltage range for CD74ACT273PW?
The CD74ACT273PW is an ACT-series device with a specified supply voltage range of 4.5V to 5.5V. Operation below 4.5V is not guaranteed - unlike AC-series variants, it does not support 3.3V or 1.8V rails. This ensures TTL-compatible input thresholds and full ±24mA output drive capability. Always use a well-bypassed 5V source with ≤100mV ripple.
Does CD74ACT273PW support hot insertion or live insertion into a powered backplane?
No, CD74ACT273PW does not support hot insertion. Its absolute maximum ratings specify no DC input voltage beyond VCC + 0.5V or below –0.5V, and no current injection outside the recommended operating conditions. Uncontrolled signal sequencing during live insertion risks latchup or permanent damage. Use power sequencing controllers or hot-swap ICs upstream if backplane insertion is required.
What is the function of the !MR pin on CD74ACT273PW, and how must it be driven?
The !MR (Master Reset) pin on CD74ACT273PW is an asynchronous, active-low input that forces all eight Q outputs to logic low (L) immediately - independent of the clock (CP) state. It must be driven to ≤0.8V for assertion and ≥2.0V for de-assertion per ACT input thresholds. A pull-up resistor to VCC is recommended when not actively driven to prevent floating and unintended reset.
Can CD74ACT273PW drive 50Ω transmission lines directly, and what layout guidance applies?
Yes, CD74ACT273PW is explicitly characterized to drive 50Ω transmission lines, verified at 85°C with 75mA sink/source current. For reliable operation, route output traces as controlled-impedance lines (50Ω ±10%), place a 0.1µF ceramic bypass capacitor within 3mm of VCC pin 20, and avoid stubs longer than 5mm to minimize reflections and ringing.
Is CD74ACT273PW pin-compatible with CD74AC273PW, and what are the key functional differences?
Yes, CD74ACT273PW and CD74AC273PW share identical TSSOP-20 pinout and core functionality. Key differences: CD74ACT273PW requires 4.5–5.5V only and guarantees ±24mA drive and TTL-compatible inputs; CD74AC273PW supports 1.5–5.5V but specifies only ±24mA typical (not min), has higher input hysteresis, and lacks guaranteed 50Ω line drive. They are not drop-in substitutes in 5V-critical designs.
CD74ACT273PW Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- 74ACT
- Package/Case:
- 20-TSSOP (0.173", 4.40mm Width)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Function:
- Master Reset
- Type:
- D-Type
- Output Type:
- Non-Inverted
- Number of Elements:
- 1
- Number of Bits per Element:
- 8
- Clock Frequency:
- 85 MHz
- Max Propagation Delay @ V, Max CL:
- 12.3ns @ 5V, 50pF
- Trigger Type:
- Positive Edge
- Current - Output High, Low:
- 24mA, 24mA
- Voltage - Supply:
- 4.5V ~ 5.5V
- Current - Quiescent (Iq):
- 8 µA
- Input Capacitance:
- 10 pF
- Operating Temperature:
- -55°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 20-TSSOP
CD74ACT273PW FAQ
1.How can I place an order for CD74ACT273PW through Aetrix?
Please submit a Request for Quotation (RFQ) for CD74ACT273PW on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for CD74ACT273PW reliable?
The price and inventory of CD74ACT273PW are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for CD74ACT273PW is usually 5 days.
3.What payment methods are accepted for CD74ACT273PW?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for CD74ACT273PW transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for CD74ACT273PW?
CD74ACT273PW orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your CD74ACT273PW order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for CD74ACT273PW?
For technical support, including CD74ACT273PW datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your CD74ACT273PW requirements.
6.How does Aetrix verify that CD74ACT273PW is sourced from the original manufacturer or authorized distributors?
All CD74ACT273PW products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that CD74ACT273PW meets industry standards.
7.What is the process for return or replacement of CD74ACT273PW?
All CD74ACT273PW units undergo pre-shipment inspection (PSI). If there is an issue with CD74ACT273PW, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The CD74ACT273PW part is unused and in its original packaging.
Return procedure for CD74ACT273PW:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
CD74ACT273PW Tags
-
SN74HC74DR
Texas Instruments

-
SN74HC74PWR
Texas Instruments

-
74LVC1G74GT,115
Nexperia USA Inc.

-
SN74LVC2G74DCUR
Texas Instruments
-
CD4013BM96
Texas Instruments

-
SN74HCT273PWR
Texas Instruments

-
SN74LVC1G74DCUR
Texas Instruments

-
SN74HC574DWR
Texas Instruments
-
74LVC1G74DC,125
Nexperia USA Inc.

-
SN74HC273DWR
Texas Instruments

-
SN74HCT574DWR
Texas Instruments

-
SN74LVC1G74DCTR
Texas Instruments
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

