Texas Instruments CD74ACT74QM96Q1
- Part No.:
- CD74ACT74QM96Q1
- Manufacturer:
- Texas Instruments
- Category:
- Flip Flops
- Package:
- 14-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
CD74ACT74QM96Q1.pdf
- Description:
- IC FF D-TYPE DUAL 1BIT 14SOIC
- Quantity:
- Payment:

- Shipping:

Inventory:2,676
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
CD74ACT74QM96Q1 from Texas Instruments is an automotive-qualified dual positive-edge-triggered D-type flip-flop with independent preset and clear inputs, 85 MHz maximum clock frequency, ±24 mA output drive, and TTL-voltage-compatible inputs. It operates across −40°C to 125°C and delivers balanced propagation delays (2.4–9.5 ns) in a 14-pin SOIC package for synchronous logic control in engine control units and ADAS domain controllers.
For engineers reviewing the CD74ACT74QM96Q1 datasheet, CD74ACT74QM96Q1 pinout, CD74ACT74QM96Q1 application, or CD74ACT74QM96Q1 equivalent, this page provides verified functional specifications, automotive-grade timing behavior, SOIC-14 terminal mapping, and validated alternative options for safety-critical digital sequencing and state-holding circuits.
Technical Context
The CD74ACT74QM96Q1 implements two independent edge-triggered D flip-flops with asynchronous active-low preset (PRE) and clear (CLR), enabling immediate state override regardless of clock or data. Each flip-flop features identical input thresholds (VIH = 2 V, VIL = 0.8 V) and supports 5-V operation only (4.5–5.5 V).
Its CMOS ACT technology delivers bipolar-speed performance (tPLH/tPHL ≤ 9.5 ns) with significantly lower quiescent current (ICC ≤ 80 µA at 25°C) than legacy F/AS/S families. The device is SCR-latchup resistant and rated for automotive AEC-Q100 Grade 1 temperature range.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage | 4.5 V to 5.5 V - fixed 5-V rail operation; no 3.3-V support. |
| Max Clock Frequency | 85 MHz - enables high-speed sampling in engine timing and sensor synchronization. |
| Propagation Delay | 2.4 ns (min) to 9.5 ns (max) - ensures deterministic setup/hold timing in multi-stage pipelines. |
| Output Drive | ±24 mA - drives 15 F-family loads directly without buffering. |
| Input Compatibility | TTL-voltage level - interfaces directly with legacy 5-V microcontrollers and logic without level shifters. |
| Operating Temperature | −40°C to +125°C - qualified per AEC-Q100 for under-hood automotive applications. |
| Quiescent Current | ≤ 80 µA at 25°C - minimizes standby power in always-on vehicle subsystems. |
Pinout & Package
CD74ACT74QM96Q1 is housed in a 14-pin SOIC (M package), 3.9 mm wide, 1.75 mm max height, RoHS-compliant with NiPdAu lead finish and MSL Level-1 rating.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 2, 3, 4, 5, 6, 13 | Inputs (1CLR, 1D, 1CLK, 1PRE, 1Q, 1Q̅, 2CLR) | Asynchronous reset, data, clock, preset, and complementary outputs for first flip-flop; second CLR shares pin 13. |
| 7 | GND | Ground reference for all internal logic and output stages. |
| 8 | VCC | Primary 5-V supply; decoupling required within 10 mm of pin. |
| 9, 10, 11, 12, 14 | Inputs/Outputs (2D, 2CLK, 2PRE, 2Q, 2Q̅) | Second flip-flop's data, clock, preset, and complementary outputs; no shared pins between sections. |
Key Features
| Feature | Design Value |
|---|---|
| Automotive Qualification | AEC-Q100 Grade 1 certified - validated for deployment in powertrain and chassis control modules. |
| Asynchronous Control | Independent PRE and CLR on each flip-flop - enables immediate state initialization or fault recovery without clock dependency. |
| High Fanout Capability | Drives up to 15 F-family logic devices - reduces need for intermediate buffers in dense control logic. |
| SCR-Latchup Resistance | CMOS process with latchup immunity - prevents destructive failure during voltage transients in automotive 12-V systems. |
| Balanced Propagation Delays | tPLH ≈ tPHL (2.4–9.5 ns) - eliminates duty-cycle distortion in clock distribution and pulse-width modulation paths. |
Applications
| Engine Control Unit (ECU) | Advanced Driver Assistance Systems (ADAS) |
|---|---|
|
Use Scenario: Synchronizing crankshaft and camshaft position signals before feeding to microcontroller ADC triggers. IC Role / Device Role / Timing Role: Dual-edge-aligned register holding phase-aligned sensor states prior to time-stamped capture. Use Value: Ensures deterministic 85-MHz sampling alignment between two critical engine timing signals under thermal stress. |
Use Scenario: Latching radar echo timestamps in pre-processing pipeline before FPGA-based FFT analysis. IC Role / Device Role / Timing Role: Edge-triggered storage element capturing precise time-of-flight markers from analog front-end comparators. Use Value: Maintains sub-5 ns timing integrity between dual radar channels during cold-start and high-temperature operation. |
| Body Control Module (BCM) | Electric Power Steering (EPS) |
|
Use Scenario: Debouncing door lock/unlock switch inputs while preserving edge-triggered interrupt generation. IC Role / Device Role / Timing Role: Asynchronous clear-enabled D flip-flop acting as metastability-hardened input synchronizer. Use Value: Eliminates spurious interrupts caused by mechanical switch bounce across −40°C to 125°C ambient range. |
Use Scenario: Capturing torque sensor zero-offset calibration pulses during EPS motor startup sequence. IC Role / Device Role / Timing Role: Preset-controlled register holding calibration enable flag until stable power rail conditions are confirmed. Use Value: Prevents erroneous torque offset application by enforcing strict power-rail readiness before state capture. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual D-type flip-flop applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74ACT74QPWRQ1 | Same ACT logic family, identical 14-pin TSSOP package, but rated for −40°C to 125°C with different MSL and marking. | Compatible in signal integrity and timing, but requires PCB footprint change from SOIC to TSSOP. | Select when board space constraints favor TSSOP and reflow profile supports MSL-1. |
| CD74HC74M96Q1 | HC-family variant: lower drive (±5.2 mA), slower max frequency (60 MHz), higher propagation delay (15 ns), same SOIC-14 package. | Suitable for non-critical timing paths where reduced power and cost outweigh speed requirements. | Choose for cost-sensitive body electronics where 85 MHz is unnecessary and 5.2 mA drive suffices. |
Compared with CD74ACT74QM96Q1, SN74ACT74QPWRQ1 offers identical logic performance in a smaller footprint but demands layout revision, while CD74HC74M96Q1 trades speed and drive strength for lower static power and cost-making it viable only where timing margins exceed 15 ns and load count stays below three HC gates.
Availability
CD74ACT74QM96Q1 is available at Aetrix Electronics and suitable for engine control units, ADAS domain controllers, body control modules, and electric power steering systems requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for CD74ACT74QM96Q1 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and automotive ICs, with over 50 years of innovation in high-reliability logic and interface solutions.
The CD74ACT74QM96Q1 belongs to TI's automotive-qualified ACT logic family, designed specifically for robust, high-speed digital control in harsh-temperature automotive environments where timing predictability and latchup immunity are mandatory.
FAQ
What is the maximum operating frequency of the CD74ACT74QM96Q1?
The CD74ACT74QM96Q1 supports a maximum clock frequency of 85 MHz across its full −40°C to +125°C operating range. This value is guaranteed under VCC = 5 V ± 0.5 V and accounts for worst-case process, voltage, and temperature corners. The CD74ACT74QM96Q1 achieves this using ACT-series CMOS architecture optimized for speed-power tradeoffs in automotive timing-critical paths.
Does the CD74ACT74QM96Q1 support 3.3-V operation?
No, the CD74ACT74QM96Q1 does not support 3.3-V operation. Its recommended operating supply voltage is strictly 4.5 V to 5.5 V, with absolute maximum ratings limiting VCC to 6 V. Attempting to operate the CD74ACT74QM96Q1 at 3.3 V will result in undefined logic behavior, insufficient noise margin, and failure to meet timing specifications including setup/hold and propagation delay.
How are the preset and clear functions implemented in the CD74ACT74QM96Q1?
The CD74ACT74QM96Q1 implements active-low asynchronous preset (PRE) and clear (CLR) inputs on each flip-flop section. When either PRE or CLR is pulled low, the corresponding Q output is forced immediately-Q = H for PRE, Q = L for CLR-regardless of clock or data state. These controls override all synchronous operations and remain effective even when the clock is inactive or floating.
Is the CD74ACT74QM96Q1 pin-compatible with standard 74ACT74 devices?
Yes, the CD74ACT74QM96Q1 is pin-compatible with industry-standard 74ACT74 logic devices in SOIC-14 packages, including the commercial CD74ACT74 and military CD54ACT74. Pin assignments for VCC, GND, CLK, D, PRE, CLR, Q, and Q̅ match JEDEC MS-012AB, enabling drop-in replacement in existing 5-V designs meeting automotive qualification requirements.
What packaging and assembly information applies to the CD74ACT74QM96Q1?
The CD74ACT74QM96Q1 is supplied in a 14-pin SOIC (M package) with NiPdAu lead finish, MSL Level-1 rating (unlimited floor life), and RoHS compliance. It ships in tape-and-reel format (2500 units per reel). The package outline conforms to JEDEC MS-012AB, with 1.27 mm pitch, 3.9 mm body width, and 1.75 mm max height-matching standard SOIC-14 footprints used in automotive PCB assembly.
CD74ACT74QM96Q1 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- 74ACT
- Package/Case:
- 14-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Function:
- Set(Preset) and Reset
- Type:
- D-Type
- Output Type:
- Complementary
- Number of Elements:
- 2
- Number of Bits per Element:
- 1
- Clock Frequency:
- 85 MHz
- Max Propagation Delay @ V, Max CL:
- 9.5ns @ 5V, 50pF
- Trigger Type:
- Positive Edge
- Current - Output High, Low:
- 24mA, 24mA
- Voltage - Supply:
- 4.5V ~ 5.5V
- Current - Quiescent (Iq):
- 4 µA
- Input Capacitance:
- 10 pF
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- Automotive
- Qualification:
- AEC-Q100
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 14-SOIC
CD74ACT74QM96Q1 FAQ
1.How can I place an order for CD74ACT74QM96Q1 through Aetrix?
Please submit a Request for Quotation (RFQ) for CD74ACT74QM96Q1 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for CD74ACT74QM96Q1 reliable?
The price and inventory of CD74ACT74QM96Q1 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for CD74ACT74QM96Q1 is usually 5 days.
3.What payment methods are accepted for CD74ACT74QM96Q1?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for CD74ACT74QM96Q1 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for CD74ACT74QM96Q1?
CD74ACT74QM96Q1 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your CD74ACT74QM96Q1 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for CD74ACT74QM96Q1?
For technical support, including CD74ACT74QM96Q1 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your CD74ACT74QM96Q1 requirements.
6.How does Aetrix verify that CD74ACT74QM96Q1 is sourced from the original manufacturer or authorized distributors?
All CD74ACT74QM96Q1 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that CD74ACT74QM96Q1 meets industry standards.
7.What is the process for return or replacement of CD74ACT74QM96Q1?
All CD74ACT74QM96Q1 units undergo pre-shipment inspection (PSI). If there is an issue with CD74ACT74QM96Q1, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The CD74ACT74QM96Q1 part is unused and in its original packaging.
Return procedure for CD74ACT74QM96Q1:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
CD74ACT74QM96Q1 Tags
-
SN74HC74DR
Texas Instruments

-
SN74HC74PWR
Texas Instruments

-
74LVC1G74GT,115
Nexperia USA Inc.

-
SN74LVC2G74DCUR
Texas Instruments
-
CD4013BM96
Texas Instruments

-
SN74HCT273PWR
Texas Instruments

-
SN74LVC1G74DCUR
Texas Instruments

-
SN74HC574DWR
Texas Instruments
-
74LVC1G74DC,125
Nexperia USA Inc.

-
SN74HC273DWR
Texas Instruments

-
SN74HCT574DWR
Texas Instruments

-
SN74LVC1G74DCTR
Texas Instruments
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
