Texas Instruments CD74HC109MG4
- Part No.:
- CD74HC109MG4
- Manufacturer:
- Texas Instruments
- Category:
- Flip Flops
- Package:
- 16-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
CD74HC109MG4.pdf
- Description:
- IC FF JK TYPE DUAL 1BIT 16SOIC
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
CD74HC109MG4 from Texas Instruments is a dual positive-edge-triggered J-K flip-flop with asynchronous active-low set (S) and reset (R) inputs, operating across 2V–6V supply range, delivering 54MHz maximum clock frequency at VCC = 5V with CL = 15pF, and supporting industrial temperature range of –55°C to +125°C. It serves as a synchronous storage element in digital control logic, state machines, and clock-domain synchronization circuits.
For engineers reviewing the CD74HC109MG4 datasheet, CD74HC109MG4 pinout, CD74HC109MG4 application, or CD74HC109MG4 equivalent, key selection considerations include its Schmitt-trigger clock inputs for noise immunity, balanced propagation delay (14ns typical at 5V), LSTTL fanout capability (10 loads), and compatibility with both CMOS and TTL-level input thresholds.
Technical Context
The CD74HC109MG4 implements two independent edge-triggered J-K flip-flops sharing no internal coupling - each responds solely to its own CP, J, K, S, and R signals. Its asynchronous S and R override clocked operation and force Q/Q outputs high or low regardless of clock phase.
Each flip-flop features Schmitt-trigger clock inputs enabling robust operation under slow-rising or noisy clock edges, and exhibits matched tPLH/tPHL propagation delays (±2ns typical mismatch) with transition times under 19ns at 5V/CL=50pF - critical for deterministic timing in sequential logic design.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Logic Family | High-speed CMOS (HC), compatible with 2V–6V supply - enables mixed-voltage system interfacing without level shifters. |
| Max Clock Frequency | 54 MHz at VCC = 5V, CL = 15pF - supports medium-speed digital control loops and data sampling up to ~18.5 ns minimum clock period. |
| Propagation Delay (CP→Q) | 14 ns typical at VCC = 5V, CL = 15pF - ensures predictable setup/hold margin in cascaded counter or register chains. |
| Input Hysteresis | Schmitt-trigger clock inputs with ~0.4V hysteresis at 5V - rejects sub-400mV noise spikes on clock lines without external filtering. |
| Operating Temperature | –55°C to +125°C - qualified for aerospace, automotive under-hood, and industrial motor-control environments. |
| Output Drive | ±25 mA per output, 10 LSTTL loads - sufficient to drive multiple downstream gates or small LED indicators directly. |
| Quiescent Current | 4 µA typical at 25°C, <80 µA max over full temp range - enables low-power standby modes in battery-backed systems. |
Pinout & Package
CD74HC109MG4 is supplied in a 16-pin SOIC (Small Outline Integrated Circuit) package with standard JEDEC MS-012AC footprint (5.3mm width, 1.27mm pitch). Pin 1 is located at the top-left corner marked by a beveled edge or dot.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (1R) | Active-low Reset for Flip-Flop 1 | Asynchronous reset: forces 1Q = H, 1Q̅ = H when low; overrides clock and J/K states. |
| 2 (1J) | Data Input J for Flip-Flop 1 | J input sampled on rising CP edge; determines toggle/set behavior per truth table. |
| 3 (1K) | Data Input K for Flip-Flop 1 | K input sampled on rising CP edge; complements J to define reset/toggle/no-change action. |
| 4 (1CP) | Clock Input for Flip-Flop 1 | Schmitt-triggered positive-edge clock - immune to slow edges; triggers state change only on clean 0→1 transition. |
| 5 (1S) | Active-low Set for Flip-Flop 1 | Asynchronous set: forces 1Q = H, 1Q̅ = H when low; higher priority than clock but lower than simultaneous S+R. |
| 6 (1Q) | True Output Q of Flip-Flop 1 | Complementary to 1Q̅; latched value after each valid CP edge or async S/R assertion. |
| 7 (GND) | Ground Reference | Primary return path for all I/O and internal logic; requires low-impedance PCB connection to minimize ground bounce. |
| 8 (1Q̅) | Inverted Output Q̅ of Flip-Flop 1 | Complement of 1Q; provides direct access to inverted state without external inverter. |
| 9 (2Q̅) | Inverted Output Q̅ of Flip-Flop 2 | Independent inverted output; enables dual-channel status monitoring or differential bus driving. |
| 10 (2Q) | True Output Q of Flip-Flop 2 | Independent true output; supports parallel data paths or mirrored control logic. |
| 11 (2S) | Active-low Set for Flip-Flop 2 | Asynchronous set for second flip-flop; electrically isolated from first channel's S input. |
| 12 (2CP) | Clock Input for Flip-Flop 2 | Independent Schmitt-triggered clock input; allows separate clock domains per flip-flop. |
| 13 (2K) | Data Input K for Flip-Flop 2 | Independent K input; enables distinct J-K configurations per channel. |
| 14 (2J) | Data Input J for Flip-Flop 2 | Independent J input; supports dual-function logic such as dual counters or redundant state registers. |
| 15 (2R) | Active-low Reset for Flip-Flop 2 | Asynchronous reset for second flip-flop; no cross-talk with 1R signal path. |
| 16 (VCC) | Positive Supply Rail | 2V–6V tolerant; decoupling capacitor (0.1µF ceramic) required within 5mm of pin for stable switching performance. |
Key Features
| Feature | Design Value |
|---|---|
| Schmitt-trigger clock inputs | Enables reliable operation with slow or noisy clocks (e.g., RC oscillators or long PCB traces) without external hysteresis components. |
| Asynchronous set/reset | Allows immediate initialization or fault recovery independent of clock timing - essential for power-on reset and safety-critical sequencing. |
| Balanced tPLH/tPHL delay | Ensures symmetrical rise/fall timing in feedback paths, reducing metastability risk in self-timed circuits and ring oscillators. |
| High noise immunity (NIL/NIH = 30% of VCC) | Rejects transient noise up to ±1.5V at 5V supply - eliminates false triggering in electrically harsh environments like motor drives. |
| Wide VCC range (2V–6V) | Supports direct interface with 3.3V microcontrollers, 5V legacy peripherals, and 2.5V FPGA I/O banks without voltage translation. |
Applications
| Industrial PLC Counter Module | Digital Power Supply Sequencing |
|---|---|
Use Scenario: Counting encoder pulses in motor position feedback loops while maintaining state during brief power interruptions. IC Role / Device Role / Timing Role: Dual J-K flip-flop acts as a 2-bit synchronous counter stage with asynchronous reset for emergency stop recovery. Use Value: Schmitt-trigger CP inputs reject EMI from brushless motor commutation; –55°C to +125°C rating ensures reliability inside sealed control cabinets. |
Use Scenario: Enabling rail-specific power-up sequences (e.g., 12V → 5V → 3.3V) with precise interlock timing and fault hold-off. IC Role / Device Role / Timing Role: Each flip-flop controls one power rail enable signal, triggered by upstream supervisor outputs and reset by overvoltage fault flags. Use Value: Independent S/R pins allow per-rail hard reset without disrupting other rails; 10 LSTTL fanout drives multiple MOSFET gate drivers directly. |
| Automotive Body Control Unit | Test Equipment Pattern Generator |
Use Scenario: Debouncing door lock/unlock switch inputs and storing actuator state across ignition cycles using backup power. IC Role / Device Role / Timing Role: Flip-flop stores last commanded state (locked/unlocked); async S/R handles wake-from-sleep initialization and crash-induced reset. Use Value: Ultra-low ICC (<80 µA max) extends battery life during sleep mode; AEC-Q100 qualification supported via CD54HC109 military variant lineage. |
Use Scenario: Generating repeating test patterns (e.g., PRBS, walking 1s) for validating high-speed serial receiver eye diagrams. IC Role / Device Role / Timing Role: Cascaded CD74HC109MG4 units form a 4-bit Johnson counter; CP driven by precision function generator. Use Value: 54 MHz fMAX supports pattern rates up to 13.5 MHz; matched propagation delays ensure minimal skew between parallel output bits. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual J-K flip-flop applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74HC109DR | Same HC logic family, identical pinout and AC/DC specs; TI's current-production SOIC-16 variant with RoHS-compliant NiPdAu lead finish. | Identical functional behavior; differs only in packaging marking and tape-and-reel configuration (DR = 2500/reel vs MG4 = tube). | Select SN74HC109DR for new designs requiring guaranteed long-term availability and modern assembly compatibility. |
| MC74HC109ADTR2G | ON Semiconductor part with same pinout and logic function; specified fMAX = 50 MHz (vs 54 MHz), wider VCC range (2–6.5V), and slightly higher ICC (100 µA max). | Acceptable for cost-sensitive industrial applications where 4 MHz margin is noncritical; not recommended for high-frequency pattern generation. | Choose MC74HC109ADTR2G only if dual-sourcing is required and timing margin permits 50 MHz operation. |
Compared with CD74HC109MG4, SN74HC109DR offers identical electrical performance with enhanced manufacturing support, while MC74HC109ADTR2G trades 4 MHz speed for broader supply tolerance and alternate supply-chain assurance - neither is pin-compatible with CD74HC109MG4's legacy tube packaging but shares the same SOIC-16 footprint and logic behavior.
Availability
CD74HC109MG4 is available at Aetrix Electronics and suitable for industrial automation, automotive body electronics, and test equipment requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for CD74HC109MG4 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and logic solutions, with over 50 years of innovation in high-reliability digital ICs.
The CD74HC109MG4 belongs to TI's legacy HC logic family - designed for robust, low-power, wide-supply-range digital control in mission-critical industrial and defense systems where timing predictability and environmental resilience are paramount.
FAQ
What is the maximum clock frequency supported by CD74HC109MG4?
The CD74HC109MG4 supports a maximum clock frequency of 54 MHz when operated at VCC = 5V with a 15 pF load capacitance and ambient temperature of 25°C. This specification is validated per the official Texas Instruments datasheet SCHS140E. At 2V supply, fMAX drops to 4 MHz; at 6V, it reaches 23 MHz over the full –55°C to +125°C range. The actual achievable frequency in a given design depends on trace capacitance, driver strength, and signal integrity.
Does CD74HC109MG4 have Schmitt-trigger inputs on all pins?
No - only the clock inputs (1CP and 2CP) feature Schmitt-trigger circuitry in the CD74HC109MG4. The J, K, S, and R inputs are standard CMOS inputs without hysteresis. This design ensures noise immunity specifically on the timing-critical clock path while maintaining conventional logic thresholds on control and data inputs for compatibility with standard logic families.
Can CD74HC109MG4 operate reliably at 3.3V supply voltage?
Yes, CD74HC109MG4 is fully specified to operate from 2V to 6V, including 3.3V nominal systems. At VCC = 3.3V, it delivers VIH(min) = 2.0V, VIL(max) = 1.3V, VOH(min) = 3.15V (CMOS load), and VOL(max) = 0.1V - ensuring solid noise margins and interoperability with 3.3V microcontrollers and FPGAs without level-shifting circuitry.
What happens when both Set and Reset are asserted low simultaneously on CD74HC109MG4?
When both S and R inputs are low simultaneously on either flip-flop in the CD74HC109MG4, both Q and Q̅ outputs are forced high - a defined, stable condition per the truth table. However, if both S and R transition high simultaneously, the resulting output state is unpredictable and unstable (metastable), as explicitly noted in the datasheet. Designers must avoid this condition using proper reset sequencing or external arbitration logic.
Is CD74HC109MG4 RoHS compliant?
Yes, CD74HC109MG4 is RoHS compliant. According to Texas Instruments' Packaging Information Addendum, the part carries "Yes" in the RoHS column and uses NiPdAu (nickel-palladium-gold) lead finish. It meets EU Directive 2011/65/EU requirements and is suitable for use in environmentally regulated commercial and industrial applications.
CD74HC109MG4 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- 74HC
- Package/Case:
- 16-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tube
- Product Status:
- Discontinued at Digi-Key
- Function:
- Set(Preset) and Reset
- Type:
- JK Type
- Output Type:
- Complementary
- Number of Elements:
- 2
- Number of Bits per Element:
- 1
- Clock Frequency:
- 60 MHz
- Max Propagation Delay @ V, Max CL:
- 30ns @ 6V, 50pF
- Trigger Type:
- Positive Edge
- Current - Output High, Low:
- 5.2mA, 5.2mA
- Voltage - Supply:
- 2V ~ 6V
- Current - Quiescent (Iq):
- 4 µA
- Input Capacitance:
- 10 pF
- Operating Temperature:
- -55°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-SOIC
CD74HC109MG4 FAQ
1.How can I place an order for CD74HC109MG4 through Aetrix?
Please submit a Request for Quotation (RFQ) for CD74HC109MG4 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for CD74HC109MG4 reliable?
The price and inventory of CD74HC109MG4 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for CD74HC109MG4 is usually 5 days.
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Once your CD74HC109MG4 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for CD74HC109MG4?
For technical support, including CD74HC109MG4 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your CD74HC109MG4 requirements.
6.How does Aetrix verify that CD74HC109MG4 is sourced from the original manufacturer or authorized distributors?
All CD74HC109MG4 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that CD74HC109MG4 meets industry standards.
7.What is the process for return or replacement of CD74HC109MG4?
All CD74HC109MG4 units undergo pre-shipment inspection (PSI). If there is an issue with CD74HC109MG4, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The CD74HC109MG4 part is unused and in its original packaging.
Return procedure for CD74HC109MG4:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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