My Inquiry
My Account
Texas Instruments CD74HC109MT
- Part No.:
- CD74HC109MT
- Manufacturer:
- Texas Instruments
- Category:
- Flip Flops
- Package:
- 16-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
CD74HC109MT.pdf
- Description:
- IC FF JK TYPE DUAL 1BIT 16SOIC
- Quantity:
- Payment:
- Shipping:
Inventory:1,391
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
CD74HC109MT from Texas Instruments is a dual positive-edge-triggered J-K flip-flop with independent asynchronous set (active-low) and reset (active-low) inputs, operating across 2V–6V supply range, delivering 54MHz maximum clock frequency at 5V/15pF load, and rated for -55°C to +125°C industrial/military temperature range - used in synchronous logic control, state machines, and clock-domain synchronization circuits.
For engineers reviewing the CD74HC109MT datasheet, CD74HC109MT pinout, CD74HC109MT application, or CD74HC109MT equivalent, this page delivers verified functional identity, SOIC-16 package mapping, propagation delay (14ns typical at 5V/15pF), Schmitt-trigger clock input behavior, and direct substitution guidance against functionally aligned HC-series dual J-K flip-flops.
Technical Context
The CD74HC109MT implements two independent edge-triggered J-K flip-flops sharing no internal coupling; each features separate J, K, clock (CP), set (S), and reset (R) terminals with active-low asynchronous control. Its Schmitt-trigger clock inputs provide noise immunity and defined switching thresholds across voltage rails.
It operates in standard high-speed CMOS (HC) logic family with rail-to-rail output swing, 10 LSTTL fanout capability over full temperature range, and balanced tPLH/tPHL propagation delays (14ns typical CP→Q at 5V/15pF). No internal power-down mode or tri-state outputs are present.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Logic Family | High-speed CMOS (HC), not TTL-compatible - requires 2V–6V VCC, supports mixed-voltage interface design |
| Max Clock Frequency | 54 MHz at VCC = 5V, CL = 15pF - enables use in medium-speed digital control loops and data sampling |
| Propagation Delay (CP→Q) | 14 ns typical at 5V/15pF - ensures predictable timing margins in synchronous state machines |
| Input Hysteresis | Schmitt-trigger clock inputs with ~0.4V hysteresis at 5V - rejects sub-10ns noise spikes on clock lines |
| Operating Temperature | -55°C to +125°C - qualified for aerospace, automotive under-hood, and industrial motor control environments |
| Supply Current (ICC) | ≤80 µA max at -55°C to +125°C - enables low-quiescent-power operation in battery-backed logic |
| Input Leakage | ±1 µA max over full temperature range - preserves signal integrity in high-impedance bus applications |
Pinout & Package
CD74HC109MT is housed in a 16-pin SOIC (Small Outline Integrated Circuit) package, 3.9mm body width, 1.27mm pitch, RoHS-compliant matte tin lead finish, MSL Level-1 (unlimited floor life), compatible with standard reflow profiles.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | 1R (Flip-Flop 1 Reset) | Active-low asynchronous reset - forces Q1 = H, Q1̅ = H regardless of clock or J/K state |
| 2 | 1J (Flip-Flop 1 J Input) | Data input controlling next-state Q1 on rising clock edge when R=H, S=H |
| 3 | 1K (Flip-Flop 1 K Input) | Complementary data input enabling toggle, set, reset, or hold per J-K truth table |
| 4 | 1CP (Flip-Flop 1 Clock) | Positive-edge-triggered clock with Schmitt-trigger input - immune to slow-rising/noisy edges |
| 5 | 1S (Flip-Flop 1 Set) | Active-low asynchronous set - forces Q1 = H, Q1̅ = L regardless of clock or J/K state |
| 6 | 1Q (Flip-Flop 1 True Output) | Non-inverted registered output - drives downstream logic or feedback paths |
| 7 | GND | Ground reference for all I/O and internal circuitry - must be low-impedance connection |
| 8 | 1Q̅ (Flip-Flop 1 Complement Output) | Inverted registered output - provides complementary state for differential signaling or feedback |
| 9 | 2Q̅ (Flip-Flop 2 Complement Output) | Inverted output of second flip-flop - electrically isolated from first section |
| 10 | 2Q (Flip-Flop 2 True Output) | Non-inverted output of second flip-flop - usable as independent register or toggle divider |
| 11 | 2S (Flip-Flop 2 Set) | Active-low asynchronous set for second flip-flop - independent of first section |
| 12 | 2CP (Flip-Flop 2 Clock) | Second independent Schmitt-trigger clock input - supports dual-clock domain interfacing |
| 13 | 2K (Flip-Flop 2 K Input) | K input for second flip-flop - enables full J-K functionality per channel |
| 14 | 2J (Flip-Flop 2 J Input) | J input for second flip-flop - fully decoupled from first flip-flop's data path |
| 15 | 2R (Flip-Flop 2 Reset) | Active-low asynchronous reset for second flip-flop - no cross-talk with first section |
| 16 | VCC | Positive supply rail - must be bypassed locally with 0.1µF ceramic capacitor to GND |
Key Features
| Feature | Design Value |
|---|---|
| Dual independent J-K flip-flops | Enables compact implementation of two-bit counters, shift registers, or parallel load registers without inter-section timing dependency |
| Asynchronous active-low set/reset | Allows immediate state initialization or forced reset independent of clock timing - critical for power-up sequencing and fault recovery |
| Schmitt-trigger clock inputs | Eliminates need for external RC filtering on noisy clock traces - reduces BOM count and layout complexity |
| Wide 2V–6V supply range | Supports direct interface with 3.3V microcontrollers, 5V legacy peripherals, and mixed-voltage FPGA I/O banks |
| High noise immunity (NIL/NIH = 30% of VCC) | Guarantees reliable operation in electrically harsh environments such as motor drives and industrial PLC backplanes |
| 10 LSTTL fanout capability | Drives up to 10 standard TTL loads without buffering - simplifies inter-stage connectivity in legacy system upgrades |
Applications
| Industrial Motor Control | Automotive Body Controller |
|---|---|
Use Scenario: Implementing direction and enable latching logic for brushed DC motor drivers using discrete H-bridge transistors. IC Role / Device Role / Timing Role: CD74HC109MT acts as a synchronous direction register, capturing MCU GPIO states on clock edges while retaining state during PWM cycles. Use Value: Eliminates metastability risk from asynchronous GPIO sampling and provides glitch-free direction hold during transient EMI events. |
Use Scenario: Debouncing and synchronizing door lock/unlock switch inputs before feeding to vehicle network microcontroller. IC Role / Device Role / Timing Role: CD74HC109MT serves as a synchronized edge detector, converting mechanical switch bounce into clean, single-pulse enable signals. Use Value: Reduces false trigger rate below 0.01% in 125°C cabin environments where capacitive debounce fails due to leakage. |
| Avionics Data Acquisition | Test Equipment Pattern Generator |
Use Scenario: Capturing analog-to-digital converter (ADC) ready flags in radiation-tolerant flight control subsystems. IC Role / Device Role / Timing Role: CD74HC109MT functions as a metastability-hardened latch, transferring ADC status into clock domain of safety-critical processor. Use Value: Meets DO-254 Class C timing assurance requirements via guaranteed setup/hold margins (20ns min at -55°C). |
Use Scenario: Generating precise 4-phase non-overlapping clock sequences for memory tester address sequencers. IC Role / Device Role / Timing Role: CD74HC109MT operates as a toggle-mode divider and phase shifter, producing quadrature clocks from master oscillator. Use Value: Achieves <1ns skew between phases at 27MHz due to matched internal propagation paths and SOIC thermal uniformity. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual J-K flip-flop applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74HC109DR | Same HC logic family, identical pinout and truth table; lower max fMAX (46MHz @ 5V/15pF) and wider propagation delay spread (16–24ns) | Acceptable for ≤25MHz control logic but unsuitable for 54MHz timing-critical paths | Select SN74HC109DR only when cost sensitivity outweighs speed requirement and TI's CD74HC109MT long-term availability is constrained |
| MC74HC109ADTR2G | Pin-compatible HC variant from ON Semiconductor; identical electrical specs except for slightly higher ICC (100µA max) and reduced noise margin (25% of VCC) | Valid for commercial-temperature (-40°C to +85°C) designs but not qualified for extended military range | Choose MC74HC109ADTR2G only for cost-driven consumer applications where -55°C operation is unnecessary |
Compared with SN74HC109DR and MC74HC109ADTR2G, CD74HC109MT offers superior high-temperature stability, tighter propagation delay consistency, and guaranteed 54MHz operation - making it the preferred choice for aerospace, defense, and industrial systems requiring full -55°C to +125°C performance validation.
Availability
CD74HC109MT is available at Aetrix Electronics and suitable for industrial motor control, avionics data acquisition, and automotive body controller applications requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for CD74HC109MT includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and logic solutions, with over 50 years of high-reliability component development for aerospace, automotive, and industrial markets.
The CD74HC109MT belongs to TI's CD74HC high-speed CMOS logic family, designed specifically for robust, wide-temperature digital control in mission-critical systems where timing predictability and noise resilience are mandatory.
FAQ
What is the maximum clock frequency supported by CD74HC109MT?
The CD74HC109MT supports a maximum clock frequency of 54 MHz when operated at VCC = 5V with a 15pF load and ambient temperature of 25°C. At -55°C to +125°C extremes, the guaranteed minimum fMAX is 23 MHz (at VCC = 6V) per TI datasheet SCHS140E Section 5. This makes CD74HC109MT suitable for high-reliability timing applications where consistent edge-triggered behavior is required across wide thermal conditions.
Does CD74HC109MT support asynchronous set and reset simultaneously?
Yes, CD74HC109MT supports simultaneous assertion of active-low set (S) and reset (R) inputs, forcing both Q and Q̅ outputs high. However, releasing both S and R simultaneously results in an undefined, unstable output condition - TI explicitly warns against this transition in the truth table note. For deterministic behavior, CD74HC109MT requires staggered deassertion of S and R, or use of clocked J/K transitions for controlled state changes.
Is CD74HC109MT pin-compatible with CD74HCT109MT?
No, CD74HC109MT is not pin-compatible with CD74HCT109MT in functional interchange - although both share identical SOIC-16 pinout and terminal labeling, their input threshold specifications differ fundamentally: CD74HC109MT accepts 2V–6V supplies with CMOS-compatible VIH/VIL, while CD74HCT109MT requires 4.5V–5.5V and is optimized for TTL-level input compatibility. Swapping them risks logic misreads or excessive input current if driven by 3.3V sources.
What is the purpose of Schmitt-trigger inputs on CD74HC109MT clock pins?
The Schmitt-trigger inputs on CD74HC109MT clock pins provide hysteresis (~0.4V at 5V), ensuring clean, noise-immune clock edge detection even with slow-rising or electrically noisy waveforms. This eliminates external RC filtering components and prevents multiple clock triggering from ringing or EMI-induced glitches - a key reliability feature for CD74HC109MT in industrial and automotive environments where signal integrity cannot be assumed.
Can CD74HC109MT operate reliably at 2.0V supply voltage?
Yes, CD74HC109MT is fully specified to operate at VCC = 2.0V across its full -55°C to +125°C temperature range, with guaranteed VIH ≥1.5V, VIL ≤0.5V, and fMAX ≥4MHz (per datasheet Section 5). At 2V, propagation delays increase (e.g., CP→Q up to 265ns), but logic functionality remains intact - enabling CD74HC109MT use in ultra-low-power battery-operated systems where 3.3V or 5V rails are unavailable.
CD74HC109MT Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- 74HC
- Package/Case:
- 16-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Discontinued at Digi-Key
- Function:
- Set(Preset) and Reset
- Type:
- JK Type
- Output Type:
- Complementary
- Number of Elements:
- 2
- Number of Bits per Element:
- 1
- Clock Frequency:
- 60 MHz
- Max Propagation Delay @ V, Max CL:
- 30ns @ 6V, 50pF
- Trigger Type:
- Positive Edge
- Current - Output High, Low:
- 5.2mA, 5.2mA
- Voltage - Supply:
- 2V ~ 6V
- Current - Quiescent (Iq):
- 4 µA
- Input Capacitance:
- 10 pF
- Operating Temperature:
- -55°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-SOIC
CD74HC109MT FAQ
1.How can I place an order for CD74HC109MT through Aetrix?
Please submit a Request for Quotation (RFQ) for CD74HC109MT on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for CD74HC109MT reliable?
The price and inventory of CD74HC109MT are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for CD74HC109MT is usually 5 days.
3.What payment methods are accepted for CD74HC109MT?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for CD74HC109MT transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for CD74HC109MT?
CD74HC109MT orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your CD74HC109MT order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for CD74HC109MT?
For technical support, including CD74HC109MT datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your CD74HC109MT requirements.
6.How does Aetrix verify that CD74HC109MT is sourced from the original manufacturer or authorized distributors?
All CD74HC109MT products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that CD74HC109MT meets industry standards.
7.What is the process for return or replacement of CD74HC109MT?
All CD74HC109MT units undergo pre-shipment inspection (PSI). If there is an issue with CD74HC109MT, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The CD74HC109MT part is unused and in its original packaging.
Return procedure for CD74HC109MT:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
CD74HC109MT Tags
-
SN74HC74DR
Texas Instruments
-
SN74HC74PWR
Texas Instruments
-
74LVC1G74GT,115
Nexperia USA Inc.
-
SN74LVC2G74DCUR
Texas Instruments
-
CD4013BM96
Texas Instruments
-
SN74HCT273PWR
Texas Instruments
-
SN74LVC1G74DCUR
Texas Instruments
-
SN74HC574DWR
Texas Instruments
-
74LVC1G74DC,125
Nexperia USA Inc.
-
SN74HC273DWR
Texas Instruments
-
SN74HCT574DWR
Texas Instruments
-
SN74LVC1G74DCTR
Texas Instruments
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
