Texas Instruments CD74HC112E

Overview

CD74HC112E from Texas Instruments is a dual J-K flip-flop with independent negative-edge-triggered clock inputs, asynchronous set (PRE) and reset (CLR), complementary Q/Q̅ outputs, and buffered inputs. It operates from 2 V to 6 V, delivers 60 MHz max clock frequency at 5 V/15 pF, supports –55°C to +125°C industrial/military temperature range, and drives 10 LSTTL loads - used in synchronous logic control, state machines, and digital counters.

For engineers reviewing the CD74HC112E datasheet, CD74HC112E pinout, CD74HC112E application, or CD74HC112E equivalent, key selection criteria include negative-edge triggering behavior, asynchronous PRE/CLR polarity (active-low), CMOS-level input compatibility (VIH = 3.15 V min @ 4.5 V), propagation delay (tPLH/tPHL = 35 ns typ @ 4.5 V), and PDIP-16 package mechanical fit for legacy through-hole designs.

Technical Context

The CD74HC112E implements two independent edge-triggered J-K flip-flops using silicon-gate CMOS technology, achieving LSTTL-equivalent speed with significantly lower static power consumption. Each section features separate J, K, CLK, PRE, and CLR inputs plus Q and Q̅ outputs, with state change occurring exclusively on the falling edge of CLK.

Asynchronous PRE and CLR override clocked operation when asserted low, forcing Q high or low respectively regardless of J/K states or clock timing. Input hysteresis improves noise immunity, while balanced propagation delays and transition times ensure predictable setup/hold timing margins across temperature and voltage.

Key Specifications

Pinout & Package

CD74HC112E uses a 16-pin plastic dual in-line package (PDIP-N) with 19.31 mm × 6.35 mm body size, 2.54 mm lead pitch, and through-hole mounting. Pin 1 is marked by a notch or dot at the top-left corner.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual J-K flip-flop applications.

Compared with CD74HCT112E and SN74HC112N, the CD74HC112E provides broader supply voltage flexibility (2–6 V vs. 4.5–5.5 V or fixed 5 V nominal), making it suitable for battery-backed or multi-rail systems where voltage headroom is constrained.

Availability

CD74HC112E is available at Aetrix Electronics and suitable for industrial PLC logic modules, digital test equipment counters, legacy instrumentation upgrades, and military data acquisition systems requiring stable component supply across extended temperature ranges and long production lifecycles.

Supply support for CD74HC112E includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and logic solutions, with over 90 years of innovation in high-reliability and industrial-grade components.

The CD74HC112E belongs to TI's legacy HC logic family, designed specifically for drop-in replacement of bipolar TTL in cost-sensitive, power-constrained, and wide-temperature industrial and defense applications.

FAQ

What is the maximum clock frequency supported by CD74HC112E?

The CD74HC112E supports a maximum clock frequency of 60 MHz when operated at VCC = 5 V with a 15 pF load, as specified in the switching characteristics table. At 2 V supply, fMAX drops to 4 MHz; at 6 V, it reaches 23 MHz under full temperature range conditions. These values reflect guaranteed performance across –55°C to +125°C.

Does CD74HC112E support asynchronous preset and clear functions?

Yes, CD74HC112E provides fully asynchronous PRE (preset) and CLR (clear) inputs for each flip-flop section. Both are active-low: asserting PRE low forces Q high regardless of clock or J/K states, while asserting CLR low forces Q low. These functions operate independently of the clock edge and take priority over synchronous inputs.

What is the recommended bypass capacitor for CD74HC112E?

Texas Instruments recommends a 0.1 μF ceramic bypass capacitor placed as close as possible to the VCC (pin 8) and GND (pin 7) pins of the CD74HC112E. For enhanced noise suppression across frequencies, a parallel combination of 0.1 μF and 1 μF capacitors is acceptable - critical for stable operation in noisy industrial environments.

Can CD74HC112E be used as a toggle flip-flop?

Yes, CD74HC112E can operate as a toggle flip-flop by connecting both J and K inputs high (J = K = VCC). On each negative clock edge, the output toggles between Q and Q̅ states. This mode is explicitly supported in the truth table and commonly used in divide-by-2 counters and clock dividers.

Is CD74HC112E pin-compatible with older 74LS112 devices?

CD74HC112E is functionally identical and pin-compatible with 74LS112 in PDIP-16 packaging, including matching pin assignments for CLK, J, K, PRE, CLR, Q, and Q̅. However, it requires no pull-up resistors, draws far less current, and operates over a wider voltage and temperature range - making it a direct upgrade path without PCB changes.