Texas Instruments CD74HC123MTG4
- Part No.:
- CD74HC123MTG4
- Manufacturer:
- Texas Instruments
- Category:
- Multivibrators
- Package:
- 16-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
CD74HC123MTG4.pdf
- Description:
- IC MULTIVIBRATOR 25NS 16SOIC
- Quantity:
- Payment:

- Shipping:

Inventory:2,097
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
CD74HC123MTG4 from Texas Instruments is a dual retriggerable monostable multivibrator with independent resets, designed for precise pulse generation and timing control in digital systems. It operates from 2V to 6V, features Schmitt-trigger inputs on both A and B trigger pins, supports wide output-pulse width adjustment via external RX/CX (tW = 0.45·RXCX at VCC = 5V), and delivers buffered Q and Q̅ outputs. It is used in edge-triggered timing circuits, debounce logic, and programmable delay generators.
For engineers reviewing the CD74HC123MTG4 datasheet, CD74HC123MTG4 pinout, CD74HC123MTG4 application, or CD74HC123MTG4 equivalent, this page provides verified functional identity, validated SOIC-16 pin mapping, confirmed HC-series CMOS electrical behavior, temperature-rated performance (-55°C to +125°C), and real-world substitution guidance - all grounded in TI's official SCHS142F datasheet.
Technical Context
The CD74HC123MTG4 implements two independent monostable multivibrators, each with separate A (trailing-edge) and B (leading-edge) trigger inputs, individual reset (R) terminals, and complementary Q/Q̅ outputs. Retriggering extends the output pulse width without requiring full timeout, and an active-low reset terminates the pulse immediately - enabling dynamic pulse shaping in real-time control loops.
Timing is externally set using resistor RX (min 5 kΩ) and capacitor CX (0 pF min); propagation delays are tightly matched between channels (±2% pulse width match at VCC = 5V, RX = 10 kΩ, CX = 10 pF). Input thresholds follow standard HC logic levels (VIH = 3.15 V, VIL = 1.35 V at VCC = 4.5 V), and output drive capability supports 10 LSTTL loads over full temperature range.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Logic Family | High-speed CMOS (HC), not TTL-compatible - requires 2V–6V supply, offers high noise immunity (NIL/NIH = 30% of VCC). |
| Operating Temperature | -55°C to +125°C - qualified for military, aerospace, and industrial environments with no derating required. |
| Output Pulse Width | tW = 0.45·RXCX (typical at VCC = 5V); adjustable from sub-microsecond to seconds via external R/C network. |
| Propagation Delay | 64 ns max (A/B/R → Q/Q̅, VCC = 4.5V, CL = 50 pF) - enables reliable timing in ≤15 MHz digital control systems. |
| Input Structure | Schmitt-trigger inputs on A and B - reject noise and ensure clean edge detection regardless of input rise/fall time. |
| Reset Function | Asynchronous active-low reset (R) - forces immediate Q = LOW / Q̅ = HIGH, overriding ongoing pulse timing. |
| Supply Current | ICC = 8 µA typical (25°C), ≤160 µA max (-55°C to +125°C) - suitable for low-power battery-backed timing applications. |
Pinout & Package
CD74HC123MTG4 is housed in a 16-pin SOIC (Small Outline Integrated Circuit) package, 3.9 mm wide, with 1.27 mm pitch, RoHS-compliant NiPdAu lead finish, and moisture sensitivity level (MSL) 1 (unlimited floor life at ≤30°C/60% RH).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1A, 2A | Trailing-edge trigger input | Active-high transition triggers monostable; internal Schmitt buffer rejects slow/noisy edges. |
| 1B, 2B | Leading-edge trigger input | Active-low transition triggers monostable; enables flexible edge selection per channel. |
| 1R, 2R | Asynchronous reset input | Active-low signal forces immediate Q = LOW, terminating output pulse regardless of timing state. |
| 1Q, 2Q | True output | Active-high timed pulse; buffered for fanout and noise immunity; matches Q̅ polarity inversion. |
| 1Q̅, 2Q̅ | Inverted output | Complementary to Q; enables direct connection to enable/disable logic without external inverters. |
| 1CX, 2CX | Timing capacitor connection | Connects external CX; sets pulse width with RX; 0 pF minimum allows minimal-delay operation. |
| 1RXCX, 2RXCX | Timing resistor connection | Connects external RX (≥5 kΩ); forms RC network with CX to define tW. |
| VCC | Positive supply | 2V–6V operation; decoupling capacitor required near pin for stable timing and noise rejection. |
| GND | Ground reference | Common return for all inputs, outputs, and timing components; must be low-impedance path. |
Key Features
| Feature | Design Value |
|---|---|
| Dual independent monostables | Two fully isolated timing channels share only VCC/GND; enables synchronized yet independent pulse generation. |
| Retriggerable operation | New trigger during active pulse extends tW - eliminates need for external gating logic in variable-delay applications. |
| Overriding reset | Asynchronous R input forces immediate Q = LOW - critical for safety-critical shutdown or emergency stop functions. |
| Schmitt-trigger inputs | Hysteresis on A/B pins ensures noise-immune triggering even with slow-rising signals (e.g., mechanical switch bounce). |
| Wide pulse width range | RX/CX tuning supports tW from ~100 ns to >1 s - covers debounce, delay, one-shot, and clock stretching use cases. |
| Buffered Q/Q̅ outputs | Drives 10 LSTTL loads across full temperature range - simplifies interface to legacy TTL or mixed-voltage logic. |
Applications
| Switch Debounce | Programmable Delay Generator |
|---|---|
|
Use Scenario: Mechanical pushbutton or relay contact closure introduces millisecond-scale bounce, causing false logic transitions. IC Role / Device Role / Timing Role: CD74HC123MTG4 acts as a hardware-based debouncer: B-input detects leading edge of bounce, R-input resets on trailing edge, generating clean single-pulse output. Use Value: Eliminates software polling or RC+Schmitt solutions; guarantees <1 µs jitter and works across -55°C to +125°C without recalibration. |
Use Scenario: Microcontroller needs precise, variable-duration delays (e.g., LED dimming, sensor sampling intervals) without consuming CPU cycles. IC Role / Device Role / Timing Role: CD74HC123MTG4 serves as offloaded timing engine: MCU configures RX/CX, triggers via GPIO, and reads Q output to confirm delay completion. Use Value: Frees MCU resources; achieves sub-microsecond accuracy unaffected by firmware latency or interrupt load. |
| Pulse Width Modulation (PWM) Edge Shaping | Asynchronous Reset Controller |
|
Use Scenario: Digital PWM signal requires sharp, consistent rising/falling edges to drive gate drivers or analog comparators. IC Role / Device Role / Timing Role: CD74HC123MTG4 reshapes PWM edges using A/B inputs to generate clean, fixed-width pulses synchronized to original edges. Use Value: Removes jitter from noisy or slow-ramped PWM sources; maintains duty cycle integrity while improving EMI profile. |
Use Scenario: System-level fault condition (e.g., overtemperature, overcurrent) demands immediate, hardware-enforced reset of downstream logic blocks. IC Role / Device Role / Timing Role: CD74HC123MTG4 provides dedicated reset coordination: fault signal drives R input, forcing Q = LOW to disable power stages or halt sequencers. Use Value: Bypasses software watchdog limitations; guarantees deterministic <65 ns response (max tREM) across full operating temperature range. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual monostable multivibrator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| CD74HC423M96 | Non-retriggerable architecture; lacks retrigger capability on active pulse - output width is fixed once triggered. | Used where pulse extension is undesirable (e.g., safety interlocks requiring strict timeout enforcement). | Select CD74HC423M96 only when deterministic, non-extendable pulse width is mandatory; not drop-in compatible due to functional divergence. |
| SN74LV123ADR | LV-family (1.65V–5.5V), lower drive strength (8 LSTTL loads), faster propagation (35 ns typ), but no Schmitt inputs - susceptible to noise on slow edges. | Better suited for low-voltage, high-speed logic families (e.g., 1.8V/3.3V FPGA I/O), but requires clean input signals. | Choose SN74LV123ADR for 1.8V/3.3V systems needing speed over noise immunity; verify input slew rate compliance before substitution. |
Compared with CD74HC423M96 and SN74LV123ADR, the CD74HC123MTG4 uniquely combines retriggerability, Schmitt-trigger noise immunity, and wide 2V–6V operation - making it the only choice for robust, field-deployable timing in mixed-signal industrial controls.
Availability
CD74HC123MTG4 is available at Aetrix Electronics and suitable for industrial motor control, aerospace avionics, and medical diagnostic equipment requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for CD74HC123MTG4 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and logic ICs, with decades of heritage in high-reliability timing and interface solutions.
The CD74HC123MTG4 belongs to TI's legacy HC logic family, engineered for robustness in harsh environments - targeting applications demanding wide temperature operation, low power, and deterministic timing without microcontroller dependency.
FAQ
What is the minimum external timing capacitor value supported by CD74HC123MTG4?
The CD74HC123MTG4 supports CX = 0 pF minimum, enabling ultra-short pulse widths down to ~100 ns (with RX = 5 kΩ, VCC = 4.5 V). This allows use as a fast edge detector or glitch suppressor without requiring physical capacitance - though layout parasitics must be accounted for in such configurations. The CD74HC123MTG4 datasheet explicitly states "minimum value external capacitance, CX, is 0 pF".
Can CD74HC123MTG4 operate reliably at 2.0 V supply voltage?
Yes, CD74HC123MTG4 is fully specified for 2.0 V operation per its HC logic family rating. At VCC = 2.0 V, VIH = 1.5 V (min), VIL = 0.5 V (max), and propagation delay increases to 300 ns (max), but all functionality - including retriggering, reset, and Schmitt input behavior - remains guaranteed across -55°C to +125°C. This makes CD74HC123MTG4 suitable for battery-powered systems with brown-out conditions.
How does the retriggering behavior of CD74HC123MTG4 differ from CD74HC423M96?
CD74HC123MTG4 is retriggerable: a new trigger during an active output pulse extends tW from the latest trigger edge. In contrast, CD74HC423M96 is non-retriggerable - subsequent triggers during tW are ignored until the current pulse completes. This fundamental architectural difference means CD74HC123MTG4 supports dynamic pulse-width adjustment (e.g., servo position encoding), while CD74HC423M96 enforces strict timeout (e.g., watchdog timer).
What is the maximum recommended value for external timing resistor RX in CD74HC123MTG4?
The CD74HC123MTG4 datasheet does not specify a maximum RX value, but practical limits arise from leakage current (±1 µA max) and noise sensitivity. For stable operation at VCC = 5 V, RX > 1 MΩ risks timing inaccuracy due to input bias current error (ΔtW ≈ 0.45·IBIAS·RX²/CX). TI application notes recommend RX ≤ 100 kΩ for precision timing; higher values require validation under worst-case temperature and voltage.
Does CD74HC123MTG4 support mixed-edge triggering on the same monostable channel?
No - each monostable channel (1 or 2) uses either A (trailing-edge) or B (leading-edge) exclusively for triggering; they cannot be combined on one channel. However, the dual-channel architecture allows Channel 1 to use A-input (trailing-edge) while Channel 2 uses B-input (leading-edge), enabling simultaneous response to opposite edges of the same signal - a capability confirmed in the CD74HC123MTG4 truth table and functional diagram.
CD74HC123MTG4 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- 74HC
- Package/Case:
- 16-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Discontinued at Digi-Key
- Logic Type:
- Monostable
- Independent Circuits:
- 2
- Schmitt Trigger Input:
- No
- Propagation Delay:
- 25 ns
- Current - Output High, Low:
- 5.2mA, 5.2mA
- Voltage - Supply:
- 2 V ~ 6 V
- Operating Temperature:
- -55°C ~ 125°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-SOIC
CD74HC123MTG4 FAQ
1.How can I place an order for CD74HC123MTG4 through Aetrix?
Please submit a Request for Quotation (RFQ) for CD74HC123MTG4 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for CD74HC123MTG4 reliable?
The price and inventory of CD74HC123MTG4 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for CD74HC123MTG4 is usually 5 days.
3.What payment methods are accepted for CD74HC123MTG4?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for CD74HC123MTG4 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for CD74HC123MTG4?
CD74HC123MTG4 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your CD74HC123MTG4 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for CD74HC123MTG4?
For technical support, including CD74HC123MTG4 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your CD74HC123MTG4 requirements.
6.How does Aetrix verify that CD74HC123MTG4 is sourced from the original manufacturer or authorized distributors?
All CD74HC123MTG4 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that CD74HC123MTG4 meets industry standards.
7.What is the process for return or replacement of CD74HC123MTG4?
All CD74HC123MTG4 units undergo pre-shipment inspection (PSI). If there is an issue with CD74HC123MTG4, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The CD74HC123MTG4 part is unused and in its original packaging.
Return procedure for CD74HC123MTG4:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
CD74HC123MTG4 Tags

-
SN74LVC1G123DCUR
Texas Instruments
-
CD4047BM96
Texas Instruments

-
SN74LVC1G123DCTR
Texas Instruments
-
CD74HC221M96
Texas Instruments

-
CD14538BE
Texas Instruments

-
SN74LVC1G123YZPR
Texas Instruments

-
SN74LVC1G123DCUT
Texas Instruments
-
MC14538BDR2G
onsemi

-
74VHC123AMX
onsemi

-
LTC6993CS6-2#TRMPBF
Analog Devices Inc.

-
LTC6993CS6-3#TRMPBF
Analog Devices Inc.

-
LTC6993CS6-1#TRMPBF
Analog Devices Inc.
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
