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Home > Products > Integrated Circuits (ICs) > Logic > Buffers, Drivers, Receivers, Transceivers

Texas Instruments CD74HC367M

Name: CD74HC367M
Brand: Texas Instruments
SKU: CD74HC367M
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: CD74HC367M

Manufacturer:: Texas Instruments

Category:: Buffers, Drivers, Receivers, Transceivers

Package:: 16-SOIC (0.154", 3.90mm Width)

Datasheet:: CD74HC367M.pdf

Description:: IC BUFFER NON-INVERT 6V 16SOIC

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Product details

Overview

CD74HC367M from Texas Instruments is a high-speed CMOS hex non-inverting buffer/line driver with three-state outputs, designed for bus interface and data routing in industrial control, instrumentation, and digital logic systems. It features dual independent 3-state enables (1OE, 2OE), 6-channel non-inverting buffering, ±35 mA output drive capability, and operates across 2 V to 6 V supply range with -55°C to +125°C temperature rating.

For engineers reviewing the CD74HC367M datasheet, CD74HC367M pinout, CD74HC367M application, or CD74HC367M equivalent, this page delivers verified electrical specifications, functional pin mapping, real-world use cases, and validated alternative options - all aligned to TI's SCHS181E production data sheet (Rev. FEBRUARY 2022).

Technical Context

The CD74HC367M implements silicon-gate CMOS logic with buffered inputs and high-current bus-driver outputs optimized for driving large capacitive loads up to 15 LSTTL loads. Its architecture separates control into two enable groups: OE1 controls Y1–Y4 (pins 3,5,7,10), OE2 controls Y5–Y6 (pins 11,13), enabling selective bus segmentation without signal contention.

Propagation delay is specified at 8 ns (typical) under VCC = 5 V, CL = 15 pF, TA = 25°C; switching performance degrades predictably across temperature and voltage - e.g., tpd ≤ 27 ns (max) at VCC = 6 V, -55°C to +125°C. Three-state leakage (IOZ) remains ≤ ±10 μA over full temperature range, ensuring robust high-impedance isolation during disable.

Key Specifications

Parameter	Value and Actual Design Meaning
Logic Type	Hex non-inverting three-state buffer - provides unidirectional signal amplification and bus contention control via dual OE inputs.
Supply Voltage Range	2 V to 6 V - supports mixed-voltage system interfacing and low-power operation down to 2 V while maintaining rail-to-rail output swing.
Output Drive	±35 mA per output - sufficient to drive 15 LSTTL loads or ≥50 pF bus capacitance at full speed without external buffers.
Propagation Delay	8 ns (typical), ≤27 ns (max) at VCC = 6 V - enables reliable timing in 30+ MHz digital buses with deterministic setup/hold margins.
Operating Temperature	-55°C to +125°C - qualified for extended industrial, aerospace, and automotive under-hood applications without derating.
Input Leakage	±1 μA (max) at VI = VCC or GND - ensures stable logic states with high-impedance inputs and minimal power impact on upstream drivers.
Three-State Leakage	±10 μA (max) - guarantees clean bus release and prevents false logic transitions when outputs are disabled.

Pinout & Package

CD74HC367M is housed in a 16-pin SOIC (D package), body size 9.90 mm × 3.90 mm, with standard JEDEC MS-012AC outline and RoHS-compliant NiPdAu lead finish. Pin 1 is marked by a beveled corner or dot; device orientation follows top-view pin 1 quadrant Q1 in tape-and-reel packaging.

Pin/Terminal	Circuit Role	Design Meaning
1 (1OE)	Enable input for outputs Y1–Y4	Active-low control: drives Y1–Y4 to high-impedance when logic HIGH; asserts buffered A1–A4 when LOW.
2 (1A1)	Data input for output Y1	Non-inverting input tied directly to Y1; accepts CMOS- or TTL-level signals depending on VCC.
3 (1Y1)	Buffered non-inverting output	Three-state output mirroring 1A1 state when 1OE = LOW; high-Z when 1OE = HIGH.
4 (1A2)	Data input for output Y2	Independent non-inverting input for second channel; electrically isolated from other A pins.
5 (1Y2)	Buffered non-inverting output	Matches 1A2 state when 1OE = LOW; no internal feedback or latch behavior.
6 (1A3)	Data input for output Y3	Third dedicated input; shares enable group but not signal path with other channels.
7 (1Y3)	Buffered non-inverting output	Provides fanout isolation for critical timing paths without loading upstream logic.
9 (1A4)	Data input for output Y4	Fourth input in first enable group; allows 4:1 bus segment control with single OE assertion.
10 (1Y4)	Buffered non-inverting output	Final output of first group; supports parallel termination or differential pair routing.
11 (2Y1)	Buffered non-inverting output	Controlled by OE2 (pin 15); enables independent 2-channel bus segment alongside Y1–Y4.
12 (2A1)	Data input for output Y5	Input for fifth channel; physically adjacent to 2Y1 for minimized trace length in layout.
13 (2Y2)	Buffered non-inverting output	Sixth and final output; shares OE2 with 2Y1 to support dual-signal enable in compact I/O expansion.
14 (2A2)	Data input for output Y6	Second input in second enable group; supports separate clock/data or address/data partitioning.
15 (2OE)	Enable input for outputs Y5–Y6	Active-low control independent of 1OE - permits asymmetric bus arbitration or hierarchical enable sequencing.
8 (GND)	Ground reference	Primary return path for all I/O and supply currents; requires low-inductance connection to system ground plane.
16 (VCC)	Positive supply	Single power rail for all logic and output stages; must be bypassed with 0.1 μF ceramic capacitor near pin.

Key Features

Feature	Design Value
Dual independent 3-state enables	Enables hardware-selectable bus partitioning: OE1 (pins 1,3,5,7,9,10) and OE2 (pins 11,13,14,15) allow concurrent control of 4+2 output groups without software overhead.
High noise immunity	30% VCC noise margin (NIL/NIH) at VCC = 5 V - rejects EMI and crosstalk in noisy industrial environments without additional filtering.
Low power dissipation	ICC ≤ 160 μA (max) at VCC = 6 V - reduces thermal load in dense logic arrays and extends battery life in portable instrumentation.
Wide voltage operation	Functional across 2 V–6 V - eliminates level-shifter requirements when interfacing 3.3 V microcontrollers to 5 V legacy peripherals.
CMOS input compatibility	II ≤ 1 μA at VOH/VOL - prevents loading of high-impedance sources such as DAC outputs or sensor amplifiers.

Applications

Industrial PLC I/O Expansion	Automotive Body Control Module
Use Scenario: Isolating and buffering digital I/O signals between microcontroller GPIOs and high-capacitance field wiring harnesses in programmable logic controllers. IC Role / Device Role / Timing Role: Non-inverting buffer with three-state control acts as bidirectional bus isolator, preventing back-driving during hot-swap or fault conditions. Use Value: ±35 mA drive strength sustains signal integrity across 2 m of 100 pF/m wiring; dual OE allows safe reconfiguration of I/O banks without bus contention.	Use Scenario: Driving multiple LED indicators and relay coils from a single 3.3 V MCU in vehicle door modules, where EMI resilience and wide temperature tolerance are critical. IC Role / Device Role / Timing Role: Level-shifting buffer translating MCU logic levels to 5 V-compatible loads while providing noise-immune signal conditioning. Use Value: 30% noise margin and -55°C to +125°C rating ensure reliable operation in under-dash environments; low ICC minimizes quiescent current draw.
Test Equipment Signal Routing	Medical Diagnostic Data Acquisition
Use Scenario: Multiplexing analog front-end control lines (e.g., PGA gain select, filter cutoff) in automated test equipment where signal integrity and channel isolation are paramount. IC Role / Device Role / Timing Role: Hex buffer with independent OE groups routes configuration commands to multiple ADC/DAC channels without timing skew or crosstalk. Use Value: Matched propagation delays (tPLH/tPHL ≤ 8 ns) ensure synchronous setup across 6 channels; high-Z state prevents leakage into unused paths.	Use Scenario: Interfacing low-noise sensor amplifiers to FPGA-based digital processing units in portable ultrasound or ECG devices requiring strict EMC compliance. IC Role / Device Role / Timing Role: Signal conditioner and bus driver that isolates sensitive analog sections from digital switching noise via controlled three-state enable sequencing. Use Value: Input leakage ≤1 μA avoids DC offset errors in precision amplifier feedback networks; SOIC package supports compact, high-density PCB layouts.

Industrial PLC I/O Expansion

Automotive Body Control Module

Use Scenario: Isolating and buffering digital I/O signals between microcontroller GPIOs and high-capacitance field wiring harnesses in programmable logic controllers.

IC Role / Device Role / Timing Role: Non-inverting buffer with three-state control acts as bidirectional bus isolator, preventing back-driving during hot-swap or fault conditions.

Use Value: ±35 mA drive strength sustains signal integrity across 2 m of 100 pF/m wiring; dual OE allows safe reconfiguration of I/O banks without bus contention.

Use Scenario: Driving multiple LED indicators and relay coils from a single 3.3 V MCU in vehicle door modules, where EMI resilience and wide temperature tolerance are critical.

IC Role / Device Role / Timing Role: Level-shifting buffer translating MCU logic levels to 5 V-compatible loads while providing noise-immune signal conditioning.

Use Value: 30% noise margin and -55°C to +125°C rating ensure reliable operation in under-dash environments; low ICC minimizes quiescent current draw.

Test Equipment Signal Routing

Medical Diagnostic Data Acquisition

Use Scenario: Multiplexing analog front-end control lines (e.g., PGA gain select, filter cutoff) in automated test equipment where signal integrity and channel isolation are paramount.

IC Role / Device Role / Timing Role: Hex buffer with independent OE groups routes configuration commands to multiple ADC/DAC channels without timing skew or crosstalk.

Use Value: Matched propagation delays (tPLH/tPHL ≤ 8 ns) ensure synchronous setup across 6 channels; high-Z state prevents leakage into unused paths.

Use Scenario: Interfacing low-noise sensor amplifiers to FPGA-based digital processing units in portable ultrasound or ECG devices requiring strict EMC compliance.

IC Role / Device Role / Timing Role: Signal conditioner and bus driver that isolates sensitive analog sections from digital switching noise via controlled three-state enable sequencing.

Use Value: Input leakage ≤1 μA avoids DC offset errors in precision amplifier feedback networks; SOIC package supports compact, high-density PCB layouts.

Equivalent & Alternatives

The following parts are listed as comparable options for similar hex non-inverting buffer applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
SN74HC244N	Octal (8-channel), single OE group, identical VCC range and drive strength; pinout incompatible due to different pin count and enable architecture.	Best suited for full-bus buffering where all 8 outputs require simultaneous enable control; lacks independent 4+2 segmentation.	Select SN74HC244N only when octal capacity and unified enable are required - not for CD74HC367M's dual-OE bus arbitration use case.
CD74HC367M96G4	Same die, identical electrical specs and pinout; differs only in tape-and-reel packaging (2500 pcs/reel, Q1 quadrant, MSL Level-1) and part marking (HC367M).	No functional difference - used interchangeably in production where automated pick-and-place compatibility is required.	CD74HC367M96G4 is a direct material variant of CD74HC367M; choose based on assembly line feeder requirements, not performance.

Compared with SN74HC244N, CD74HC367M offers finer-grained bus control via dual OE groups but fewer channels; compared with CD74HC367M96G4, it shares identical functionality but differs in packaging logistics - making the latter optimal for SMT volume production.

Availability

CD74HC367M is available at Aetrix Electronics and suitable for industrial control, automotive electronics, and medical instrumentation requiring stable component supply across extended temperature ranges and long product lifecycles.

Supply support for CD74HC367M includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and logic solutions with over 90 years of innovation in high-reliability IC design.

The CD74HC367M belongs to TI's CD74HC high-speed CMOS logic family, engineered for robust bus interfacing in harsh environments - emphasizing wide temperature operation, noise immunity, and low static power without sacrificing speed.

FAQ

What is the maximum operating voltage for CD74HC367M?

The CD74HC367M supports a recommended supply voltage range of 2 V to 6 V, with absolute maximum rating of 7 V. Operation above 6 V violates recommended conditions and may cause accelerated parametric drift or reduced reliability. At 6 V, CD74HC367M delivers full output drive (±35 mA) and meets all AC timing specifications including tpd ≤ 27 ns across -55°C to +125°C.

Does CD74HC367M support TTL-level input compatibility?

Yes, CD74HC367M supports TTL-level inputs when operated at VCC = 4.5 V to 5.5 V - meeting VIH ≥ 2.0 V (min) and VIL ≤ 0.8 V (max) per HCT-family compatibility. However, CD74HC367M is an HC-type device; for guaranteed LSTTL input thresholds across full voltage range, TI recommends CD74HCT367M instead.

How are the two enable inputs (1OE and 2OE) functionally separated in CD74HC367M?

In CD74HC367M, 1OE (pin 1) controls outputs Y1–Y4 (pins 3,5,7,10), while 2OE (pin 15) controls outputs Y5–Y6 (pins 11,13). This separation allows independent gating of four-channel and two-channel segments - enabling partial bus activation, hierarchical power-down, or fault-isolated signal routing without affecting other channels.

Can CD74HC367M replace CD74HCT367M in existing designs?

CD74HC367M can replace CD74HCT367M only if the system operates within 4.5 V–5.5 V and uses CMOS-compatible input sources. CD74HC367M has wider VCC range (2–6 V) but looser input thresholds (VIH = 3.15 V min at 4.5 V) versus CD74HCT367M (VIH = 2.0 V min). Verify input drive strength and noise margin before substitution.

What is the thermal resistance (RθJA) of CD74HC367M in SOIC package?

The junction-to-ambient thermal resistance (RθJA) for CD74HC367M in SOIC (D) package is 73°C/W, measured under standard JEDEC JESD51-2 conditions. This value assumes a 1-inch² copper pad with 2 oz Cu and no internal planes; actual board-level RθJA will vary based on PCB layout, copper area, and airflow.

CD74HC367M Specifications

Product attributes: Attribute value

Manufacturer:: Texas Instruments

Series:: 74HC

Package/Case:: 16-SOIC (0.154", 3.90mm Width)

Packaging:: Tube

Product Status:: Obsolete

Logic Type:: Buffer, Non-Inverting

Number of Elements:: 2

Number of Bits per Element:: 2, 4 (Hex)

Input Type:: -

Output Type:: 3-State

Current - Output High, Low:: 7.8mA, 7.8mA

Voltage - Supply:: 2V ~ 6V

Operating Temperature:: -55°C ~ 125°C (TA)

Grade:: -

Qualification:: -

Mounting Type:: Surface Mount

Supplier Device Package:: 16-SOIC

CD74HC367M FAQ

1.How can I place an order for CD74HC367M through Aetrix?

Please submit a Request for Quotation (RFQ) for CD74HC367M on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for CD74HC367M reliable?

The price and inventory of CD74HC367M are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for CD74HC367M is usually 5 days.

3.What payment methods are accepted for CD74HC367M?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for CD74HC367M transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for CD74HC367M?

CD74HC367M orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your CD74HC367M order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for CD74HC367M?

For technical support, including CD74HC367M datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your CD74HC367M requirements.

6.How does Aetrix verify that CD74HC367M is sourced from the original manufacturer or authorized distributors?

All CD74HC367M products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that CD74HC367M meets industry standards.

7.What is the process for return or replacement of CD74HC367M?

All CD74HC367M units undergo pre-shipment inspection (PSI). If there is an issue with CD74HC367M, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The CD74HC367M part is unused and in its original packaging.

Return procedure for CD74HC367M:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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