Texas Instruments CD74HC423M96G4
- Part No.:
- CD74HC423M96G4
- Manufacturer:
- Texas Instruments
- Category:
- Multivibrators
- Package:
- 16-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
CD74HC423M96G4.pdf
- Description:
- IC MULTIVIBRATOR 25NS 16SOIC
- Quantity:
- Payment:

- Shipping:

Inventory:3,089
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
CD74HC423M96G4 from Texas Instruments is a dual retriggerable monostable multivibrator with independent resets, designed for precise pulse generation and timing control in digital systems. It operates from 2V to 6V, features Schmitt-trigger inputs on both A and B trigger pins, supports output pulse widths from microseconds to seconds via external RX/CX components, and delivers buffered Q and Q outputs. It is used in debounce circuits, event timing, and programmable delay generators.
For engineers reviewing the CD74HC423M96G4 datasheet, CD74HC423M96G4 pinout, CD74HC423M96G4 application, or CD74HC423M96G4 equivalent, key selection considerations include its non-retriggerable reset behavior (vs. 123-series), wide temperature range (–55°C to +125°C), SOIC-16 package compatibility, and HC logic family characteristics including high noise immunity and low power consumption.
Technical Context
The CD74HC423M96G4 implements two independent monostable multivibrators, each with separate A (trailing-edge) and B (leading-edge) trigger inputs and dedicated R reset inputs. Triggering occurs at defined voltage thresholds-not edge rate-due to integrated Schmitt triggers, ensuring robust noise rejection. Pulse width tW = 0.45 × RXCX at VCC = 5V, with minimum RX = 5 kΩ and CX ≥ 0 pF.
Unlike the '123 family, the '423 series does not support negative-to-positive reset pulse triggering; reset must be held LOW to terminate the output pulse. Each monostable can be retriggered during its active period to extend the Q/Q pulse, and unused inputs must be terminated to VCC or GND to prevent floating states.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Logic Family | High-speed CMOS (HC), compatible with 2V–6V supply; enables direct interface with mixed-voltage logic systems. |
| Operating Temperature | –55°C to +125°C; supports deployment in harsh industrial, aerospace, and automotive under-hood environments. |
| Output Pulse Width Range | Configurable from µs to seconds via external RX/CX; tW = 0.45 × RXCX at 5V; allows flexible timing without firmware intervention. |
| Input Thresholds | Schmitt-trigger A/B inputs with hysteresis; ensures reliable triggering despite slow or noisy input edges. |
| Reset Behavior | Active-Low asynchronous reset (R); terminates Q/Q output immediately-no propagation delay dependency on timing state. |
| Propagation Delay | 64 ns max (A/B/R → Q/Q, VCC = 4.5V, CL = 50 pF); enables sub-100 ns timing precision in critical control paths. |
| Supply Current | 160 µA max (–55°C to +125°C, VCC = 6V); supports ultra-low-power operation in battery-backed or energy-constrained systems. |
Pinout & Package
CD74HC423M96G4 is housed in a 16-pin SOIC (D) package, 7.5 mm × 10.3 mm body size, 1.27 mm pitch, RoHS-compliant NIPDAU lead finish, MSL Level-1, tape-and-reel packaging (2500 units/reel).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1A, 2A | Trailing-edge trigger input | Activates monostable on falling edge; internal Schmitt trigger rejects noise and accommodates slow transitions. |
| 1B, 2B | Leading-edge trigger input | Activates monostable on rising edge; enables edge-selective timing control per channel. |
| 1R, 2R | Asynchronous reset input | Active-Low signal forces immediate termination of Q/Q output; no timing dependency on current pulse state. |
| 1Q, 2Q | Inverted output | Complementary buffered output; drives up to 10 LSTTL loads over full temperature range. |
| 1Q, 2Q | Non-inverted output | Buffered true output; provides rail-to-rail swing and fanout capability matching inverted output. |
| 1CX, 2CX | External timing capacitor connection | Connects to external capacitor (CX) to set pulse width; 0 pF minimum enables shortest possible timing. |
| 1RXCX, 2RXCX | External timing resistor connection | Connects to external resistor (RX ≥ 5 kΩ); defines time constant with CX for predictable tW. |
| VCC, GND | Power supply terminals | Single 2V–6V supply; decoupling required near VCC pin to maintain switching integrity and noise immunity. |
Key Features
| Feature | Design Value |
|---|---|
| Dual independent monostables | Enables two distinct timing functions on one IC-e.g., delay + timeout-with no shared timing resource contention. |
| Retriggerable operation | Allows dynamic extension of output pulse width by new trigger events before expiration-ideal for watchdog or activity-sensing applications. |
| Separate A/B edge-select inputs | Eliminates need for external edge-detection logic; simplifies design of bidirectional pulse capture or direction-sensitive timing. |
| Overriding active-Low reset | Provides deterministic, immediate pulse termination regardless of current monostable state-critical for safety-critical or fault-clearing logic. |
| Wide VCC range (2V–6V) | Supports interoperability across 3.3V, 5V, and mixed-supply systems without level-shifting circuitry. |
Applications
| Industrial Debounce Circuit | Programmable Delay Generator |
|---|---|
Use Scenario: Mechanical switch inputs in PLC I/O modules generate contact bounce lasting 1–10 ms, causing false interrupts in microcontroller systems. IC Role / Device Role / Timing Role: CD74HC423M96G4 acts as hardware-based debouncer-each monostable triggered by switch closure (B input) and reset by release (R input), generating clean, jitter-free logic pulses. Use Value: Eliminates software polling or timer-based debounce routines; reduces MCU interrupt load and guarantees <10 µs response latency independent of firmware execution. | Use Scenario: A test instrument requires user-configurable delays (10 µs to 100 ms) between stimulus and measurement sampling. IC Role / Device Role / Timing Role: CD74HC423M96G4 serves as analog-free, digitally programmable delay element-RX/CX values selected via DIP switches or jumpers to set tW. Use Value: Achieves stable, temperature-compensated delay without op-amps or RC integrators; avoids drift and component aging effects inherent in analog solutions. |
| Event Timing Monitor | Pulse Width Modulator Interface |
Use Scenario: Motor controller detects overcurrent events and must log time duration between fault onset and shutdown command. IC Role / Device Role / Timing Role: CD74HC423M96G4 captures fault pulse width-triggered by overcurrent comparator output (A input), terminated by shutdown signal (R input). Use Value: Provides hardware-accurate timestamping with ±2% pulse width match between channels; enables post-fault diagnostics without real-time OS overhead. | Use Scenario: Digital audio amplifier uses PWM input but requires synchronized enable gating aligned to carrier zero-crossings. IC Role / Device Role / Timing Role: CD74HC423M96G4 generates precisely timed gate window-triggered by zero-crossing detector (B input), reset by PWM frame sync (R input). Use Value: Ensures amplifier enable only during safe conduction intervals; prevents shoot-through and EMI spikes caused by misaligned switching edges. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar monostable multivibrator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| CD74HC123M96G4 | Supports retriggerable reset (negative-to-positive edge on R); otherwise identical pinout, timing, and electrical specs. | Preferred where reset must be edge-triggered rather than level-held; e.g., synchronous system reset coordination. | Select CD74HC123M96G4 only if reset edge sensitivity is required; CD74HC423M96G4 offers simpler level-driven reset control. |
| SN74LV123ADR | LV-family (1.65V–5.5V), lower drive strength (8 LSTTL loads), faster propagation (22 ns typ), no Schmitt inputs on A/B. | Better suited for low-voltage, high-speed logic interfacing; unsuitable for noisy or slow-edge environments due to missing hysteresis. | Choose SN74LV123ADR for 1.8V/3.3V systems requiring speed over noise immunity; retain CD74HC423M96G4 for industrial-grade robustness. |
Compared with CD74HC123M96G4, the CD74HC423M96G4 provides deterministic level-sensitive reset control ideal for fault-clearing logic, while SN74LV123ADR trades Schmitt inputs and wide VCC range for lower voltage operation and higher speed-making it suitable only in clean, low-voltage digital subsystems.
Availability
CD74HC423M96G4 is available at Aetrix Electronics and suitable for industrial automation, aerospace avionics, and test equipment applications requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for CD74HC423M96G4 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and logic solutions for industrial, automotive, and communications markets.
The CD74HC423M96G4 belongs to TI's legacy HC logic portfolio, engineered for high-noise-immunity, wide-temperature, and low-power timing applications where reliability and predictability outweigh raw speed.
FAQ
What is the function of the A and B inputs on the CD74HC423M96G4?
The A input on the CD74HC423M96G4 responds to the trailing (falling) edge of a signal, while the B input responds to the leading (rising) edge. Both feature Schmitt-trigger circuitry to reject noise and ensure consistent triggering regardless of input slew rate. This dual-edge capability allows flexible timing control without external edge-detection logic, and both inputs are fully independent per monostable channel.
How does the reset functionality differ between CD74HC423M96G4 and CD74HC123M96G4?
The CD74HC423M96G4 uses an active-Low level-sensitive reset: holding R LOW terminates the output pulse immediately. In contrast, CD74HC123M96G4 accepts a negative-to-positive edge on R to trigger reset. This makes CD74HC423M96G4 simpler for level-driven fault-clearing applications, while CD74HC123M96G4 suits synchronous edge-coordinated systems. Pinout and timing parameters remain identical.
Can CD74HC423M96G4 operate at 3.3V supply voltage?
Yes, CD74HC423M96G4 operates across 2V to 6V, making 3.3V fully supported. At VCC = 3.3V, VIH ≈ 2.31V (min), VIL ≈ 0.99V (max), and output drive remains sufficient for 3.3V LVTTL or CMOS loads. Propagation delay increases slightly versus 5V operation (e.g., ~85 ns max vs. 64 ns), but all timing specifications-including pulse width accuracy-are guaranteed across the full voltage range.
What is the minimum external timing capacitor value for CD74HC423M96G4?
The minimum external timing capacitor (CX) for CD74HC423M96G4 is 0 pF, as confirmed in the datasheet Absolute Maximum Ratings and Timing section. With CX = 0 pF and RX = 5 kΩ, the device achieves its shortest guaranteed pulse width (~2.25 µs at VCC = 5V). For stable operation, TI recommends using ≥10 pF in production designs to mitigate stray capacitance effects and improve repeatability.
Is CD74HC423M96G4 pin-compatible with CD74HC423M96?
Yes, CD74HC423M96G4 is pin-compatible with CD74HC423M96. Both use the same SOIC-16 (D) package, identical pinout, thermal profile (MSL Level-1), and marking (HC423M). The "G4" suffix denotes TI's green (lead-free, RoHS-compliant) packaging standard with NIPDAU finish, whereas "M96" alone may refer to legacy or alternate finish variants-but electrical and mechanical compatibility is maintained across all CD74HC423M96x variants.
CD74HC423M96G4 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- 74HC
- Package/Case:
- 16-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Logic Type:
- Monostable
- Independent Circuits:
- 2
- Schmitt Trigger Input:
- No
- Propagation Delay:
- 25 ns
- Current - Output High, Low:
- 5.2mA, 5.2mA
- Voltage - Supply:
- 2 V ~ 6 V
- Operating Temperature:
- -55°C ~ 125°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-SOIC
CD74HC423M96G4 FAQ
1.How can I place an order for CD74HC423M96G4 through Aetrix?
Please submit a Request for Quotation (RFQ) for CD74HC423M96G4 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for CD74HC423M96G4 reliable?
The price and inventory of CD74HC423M96G4 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for CD74HC423M96G4 is usually 5 days.
3.What payment methods are accepted for CD74HC423M96G4?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for CD74HC423M96G4 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for CD74HC423M96G4?
CD74HC423M96G4 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your CD74HC423M96G4 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for CD74HC423M96G4?
For technical support, including CD74HC423M96G4 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your CD74HC423M96G4 requirements.
6.How does Aetrix verify that CD74HC423M96G4 is sourced from the original manufacturer or authorized distributors?
All CD74HC423M96G4 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that CD74HC423M96G4 meets industry standards.
7.What is the process for return or replacement of CD74HC423M96G4?
All CD74HC423M96G4 units undergo pre-shipment inspection (PSI). If there is an issue with CD74HC423M96G4, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The CD74HC423M96G4 part is unused and in its original packaging.
Return procedure for CD74HC423M96G4:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
CD74HC423M96G4 Tags

-
SN74LVC1G123DCUR
Texas Instruments
-
CD4047BM96
Texas Instruments

-
SN74LVC1G123DCTR
Texas Instruments
-
CD74HC221M96
Texas Instruments

-
CD14538BE
Texas Instruments

-
SN74LVC1G123YZPR
Texas Instruments

-
SN74LVC1G123DCUT
Texas Instruments
-
MC14538BDR2G
onsemi

-
74VHC123AMX
onsemi

-
LTC6993CS6-2#TRMPBF
Analog Devices Inc.

-
LTC6993CS6-3#TRMPBF
Analog Devices Inc.

-
LTC6993CS6-1#TRMPBF
Analog Devices Inc.
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
