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Home > Products > Integrated Circuits (ICs) > Logic > Flip Flops

Texas Instruments CD74HC73EG4

Name: CD74HC73EG4
Brand: Texas Instruments
SKU: CD74HC73EG4
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: CD74HC73EG4

Manufacturer:: Texas Instruments

Category:: Flip Flops

Package:: 14-DIP (0.300", 7.62mm)

Datasheet:: CD74HC73EG4.pdf

Description:: IC FF JK TYPE DUAL 1BIT 14DIP

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Product details

Overview

CD74HC73EG4 from Texas Instruments is a dual J-K flip-flop with asynchronous reset, negative-edge clock triggering, complementary Q/Q̅ outputs, and buffered inputs - designed for synchronous logic control in digital systems operating from 2 V to 6 V. It delivers 60 MHz maximum clock frequency at 5 V/15 pF, supports –55°C to +125°C industrial/military temperature range, and drives up to 10 LSTTL loads.

For engineers reviewing the CD74HC73EG4 datasheet, CD74HC73EG4 pinout, CD74HC73EG4 application, or CD74HC73EG4 equivalent, key selection criteria include its HC-family CMOS voltage range (2–6 V), guaranteed negative-edge-triggered toggle behavior, hysteresis-enhanced clock noise immunity, and PDIP-14 package compatibility with legacy through-hole logic designs.

Technical Context

The CD74HC73EG4 implements two independent edge-triggered J-K flip-flops sharing no internal coupling - each with dedicated J, K, CLK, and asynchronous RESET inputs plus Q and Q̅ outputs. Its silicon-gate CMOS architecture enables LSTTL-equivalent speed with significantly lower static power consumption than bipolar logic.

Operation requires strict adherence to setup/hold timing (e.g., t_SU = 16 ns min at 4.5 V, t_H = 3 ns), and propagation delays are symmetric (t_PLH/t_PHL ≤ 48 ns at 4.5 V/50 pF). Input hysteresis improves noise margin, while fanout capability (10 LSTTL loads) ensures robust signal distribution without buffering.

Key Specifications

Parameter	Value and Actual Design Meaning
Logic Family	HC-series CMOS - operates from 2 V to 6 V, compatible with mixed-voltage systems and low-power battery-powered logic.
Max Clock Frequency	60 MHz at V_CC = 5 V, C_L = 15 pF - enables high-speed state sequencing in counters, shift registers, and control FSMs.
Propagation Delay	≤48 ns (CP to Q, 4.5 V/50 pF) - ensures predictable timing margins in synchronous pipelines with tight cycle budgets.
Operating Temperature	–55°C to +125°C - qualified for aerospace, automotive under-hood, and industrial environments requiring extended thermal stability.
Input Hysteresis	Present on clock inputs - raises effective noise immunity and tolerates slower rise/fall times without false triggering.
Fanout Capability	10 LSTTL loads - eliminates need for intermediate buffers when driving multiple downstream TTL-compatible inputs.
Supply Current (I_CC)	≤80 μA at 25°C (V_CC = 6 V) - supports ultra-low-quiescent-power operation in always-on monitoring circuits.

Pinout & Package

CD74HC73EG4 is supplied in a 14-pin plastic dual in-line package (PDIP-N), with 19.31 mm × 6.35 mm body size, 2.54 mm lead pitch, and through-hole mounting compatibility.

Pin/Terminal	Circuit Role	Design Meaning
1	1Q̅	Inverted output of first flip-flop - provides complementary logic level for differential signaling or active-low enable paths.
2	1Q	True output of first flip-flop - used directly for state feedback, counting, or register storage.
3	1J	Data input for set condition of first flip-flop - high + clock edge sets Q = 1 if K = 0.
4	2CLK	Clock input for second flip-flop - negative-edge sensitive; triggers state change only on falling transition.
5	2J	Data input for set condition of second flip-flop - functions identically to Pin 3 but for independent second stage.
6	2K	Data input for reset condition of second flip-flop - low + clock edge resets Q = 0 if J = 0.
7	GND	Ground reference - must be connected to system common; decoupling capacitor (0.1 µF) required adjacent to Pin 7.
8	2Q̅	Inverted output of second flip-flop - enables dual-channel complementary output routing without external inverters.
9	2Q	True output of second flip-flop - supports parallel data latching or dual-bit register applications.
10	2R̅	Asynchronous reset (active-low) for second flip-flop - forces Q = 0 regardless of clock or J/K state.
11	1CLK	Clock input for first flip-flop - negative-edge triggered; identical timing behavior to Pin 4.
12	1K	Data input for reset condition of first flip-flop - completes J-K functionality for first stage.
13	1R̅	Asynchronous reset (active-low) for first flip-flop - independent reset control enables staggered initialization.
14	V_CC	Positive supply rail - accepts 2–6 V DC; requires local 0.1 µF ceramic bypass capacitor to minimize switching noise.

Key Features

Feature	Design Value
Negative-edge clock triggering	Ensures deterministic state transitions synchronized to falling edges - critical for glitch-free sampling in master-slave architectures.
Asynchronous active-low reset	Allows immediate, clock-independent initialization of each flip-flop - essential for power-up clearing and fault recovery sequences.
Complementary Q/Q̅ outputs	Eliminates need for external inverters in toggle-mode or differential bus drivers - reduces component count and layout area.
Input hysteresis on clock pins	Increases effective noise margin by ~30% of V_CC, enabling reliable operation in electrically noisy industrial environments.
Wide 2–6 V supply range	Supports direct interface with 3.3 V microcontrollers, 5 V legacy peripherals, and battery-backed 2 V sensor interfaces.

Applications

Industrial Control Sequencing	Digital Test Equipment
Use Scenario: Implementing multi-step machine state machines in PLC I/O modules where precise step advancement is required on encoder-index pulses. IC Role / Device Role / Timing Role: Dual J-K flip-flop acts as a 2-bit synchronous counter and sequencer, with independent reset enabling emergency stop override. Use Value: Negative-edge triggering aligns state changes with clean falling edges of industrial encoder signals, minimizing metastability risk.	Use Scenario: Generating precise stimulus patterns in automated test equipment for validating combinational logic response timing. IC Role / Device Role / Timing Role: Provides synchronized, repeatable toggle and hold states to drive DUT inputs with known setup/hold compliance. Use Value: Guaranteed 16 ns minimum setup time and 3 ns hold time ensure valid timing windows for high-speed pattern generation.
Legacy System Logic Upgrade	Space-Constrained Embedded Counters
Use Scenario: Replacing obsolete 74LS73 in retro-computing restoration projects or military avionics spares where footprint and pinout must match. IC Role / Device Role / Timing Role: Drop-in functional replacement delivering identical truth table behavior and PDIP-14 mechanical fit. Use Value: HC logic family reduces power draw by >90% versus LS equivalents while maintaining full LSTTL load-driving capability.	Use Scenario: Building compact 2-bit binary counters in battery-powered IoT sensor nodes where board space and quiescent current are constrained. IC Role / Device Role / Timing Role: Functions as a low-power divide-by-4 counter using toggle mode (J=K=1), driven by RTC or wake-up timer. Use Value: 80 μA max ICC at 6 V enables years of operation on coin-cell batteries in sleep-wake cycling applications.

Industrial Control Sequencing

Digital Test Equipment

Use Scenario: Implementing multi-step machine state machines in PLC I/O modules where precise step advancement is required on encoder-index pulses.

IC Role / Device Role / Timing Role: Dual J-K flip-flop acts as a 2-bit synchronous counter and sequencer, with independent reset enabling emergency stop override.

Use Value: Negative-edge triggering aligns state changes with clean falling edges of industrial encoder signals, minimizing metastability risk.

Use Scenario: Generating precise stimulus patterns in automated test equipment for validating combinational logic response timing.

IC Role / Device Role / Timing Role: Provides synchronized, repeatable toggle and hold states to drive DUT inputs with known setup/hold compliance.

Use Value: Guaranteed 16 ns minimum setup time and 3 ns hold time ensure valid timing windows for high-speed pattern generation.

Legacy System Logic Upgrade

Space-Constrained Embedded Counters

Use Scenario: Replacing obsolete 74LS73 in retro-computing restoration projects or military avionics spares where footprint and pinout must match.

IC Role / Device Role / Timing Role: Drop-in functional replacement delivering identical truth table behavior and PDIP-14 mechanical fit.

Use Value: HC logic family reduces power draw by >90% versus LS equivalents while maintaining full LSTTL load-driving capability.

Use Scenario: Building compact 2-bit binary counters in battery-powered IoT sensor nodes where board space and quiescent current are constrained.

IC Role / Device Role / Timing Role: Functions as a low-power divide-by-4 counter using toggle mode (J=K=1), driven by RTC or wake-up timer.

Use Value: 80 μA max ICC at 6 V enables years of operation on coin-cell batteries in sleep-wake cycling applications.

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual J-K flip-flop applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
SN74HC73N	Same HC logic family, identical pinout and electrical specs; manufactured by TI with different packaging suffix (N vs EG4).	No functional difference - both are PDIP-14, RoHS-compliant, –55°C to +125°C rated.	Select SN74HC73N if standard TI part numbering is preferred; CD74HC73EG4 indicates G4-grade green packaging compliance.
CD74HCT73E	TTL-compatible input thresholds (VIH = 2 V min, VIL = 0.8 V max); same pinout and function but narrower 4.5–5.5 V supply range.	Better suited for mixed 5 V TTL/CMOS systems where input voltage compatibility with legacy LSTTL is mandatory.	Choose CD74HCT73E only when interfacing directly with 5 V TTL outputs; otherwise CD74HC73EG4 offers wider voltage flexibility.

Compared with SN74HC73N and CD74HCT73E, CD74HC73EG4 provides optimal balance of wide supply range (2–6 V), full military-grade temperature support, and green packaging - making it ideal for new designs requiring long-term availability and environmental compliance without sacrificing logic compatibility.

Availability

CD74HC73EG4 is available at Aetrix Electronics and suitable for industrial control sequencing, digital test equipment, legacy system logic upgrades, and space-constrained embedded counters requiring stable component supply across extended temperature ranges.

Supply support for CD74HC73EG4 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and logic solutions with over 50 years of innovation in high-reliability logic families.

The CD74HC73EG4 belongs to TI's CD74HC logic series - engineered for low-power, wide-voltage-range digital control in harsh-environment applications including aerospace, defense, and industrial automation.

FAQ

What is the maximum clock frequency supported by CD74HC73EG4?

The CD74HC73EG4 supports a maximum clock frequency of 60 MHz when operated at V_CC = 5 V with a 15 pF load. At 50 pF load, the maximum frequency drops to 30 MHz over the full temperature range (–55°C to +125°C). This performance is specified under controlled conditions per TI's SCHS134G datasheet.

Does CD74HC73EG4 support asynchronous reset functionality?

Yes, CD74HC73EG4 features independent asynchronous active-low reset inputs (1R̅ and 2R̅) for each flip-flop. Asserting either R̅ pin low immediately forces the corresponding Q output to logic low, regardless of clock or J/K input states - enabling immediate state clearing without waiting for clock edges.

What package type is used for CD74HC73EG4?

CD74HC73EG4 is packaged in a 14-pin plastic dual in-line package (PDIP-N), with dimensions of 19.31 mm × 6.35 mm and 2.54 mm lead pitch. It is RoHS-compliant, lead-free (NIPDAU finish), and rated for through-hole assembly in high-reliability applications.

Can CD74HC73EG4 operate at 3.3 V supply voltage?

Yes, CD74HC73EG4 is fully specified to operate across 2 V to 6 V, including 3.3 V. At 3.3 V, it maintains guaranteed logic thresholds (VIH ≥ 2.1 V, VIL ≤ 1.1 V), 10 LSTTL load drive capability, and –55°C to +125°C operation - making it suitable for mixed-voltage 3.3 V/5 V system interfaces.

How does the input hysteresis on CD74HC73EG4 improve system reliability?

The input hysteresis on CD74HC73EG4 clock pins increases noise immunity by approximately 30% of V_CC, effectively widening the voltage threshold window between logic high and low recognition. This prevents false triggering from EMI-induced ringing or slow-rising signals - especially valuable in motor control, power supply monitoring, and industrial sensor interfaces.

CD74HC73EG4 Specifications

Product attributes: Attribute value

Manufacturer:: Texas Instruments

Series:: 74HC

Package/Case:: 14-DIP (0.300", 7.62mm)

Packaging:: Tube

Product Status:: Discontinued at Digi-Key

Function:: Reset

Type:: JK Type

Output Type:: Complementary

Number of Elements:: 2

Number of Bits per Element:: 1

Clock Frequency:: 60 MHz

Max Propagation Delay @ V, Max CL:: 28ns @ 6V, 50pF

Trigger Type:: Negative Edge

Current - Output High, Low:: 5.2mA, 5.2mA

Voltage - Supply:: 2V ~ 6V

Current - Quiescent (Iq):: 4 µA

Input Capacitance:: 10 pF

Operating Temperature:: -55°C ~ 125°C (TA)

Grade:: -

Qualification:: -

Mounting Type:: Through Hole

Supplier Device Package:: 14-PDIP

CD74HC73EG4 FAQ

1.How can I place an order for CD74HC73EG4 through Aetrix?

Please submit a Request for Quotation (RFQ) for CD74HC73EG4 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for CD74HC73EG4 reliable?

The price and inventory of CD74HC73EG4 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for CD74HC73EG4 is usually 5 days.

3.What payment methods are accepted for CD74HC73EG4?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for CD74HC73EG4 transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for CD74HC73EG4?

CD74HC73EG4 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your CD74HC73EG4 order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for CD74HC73EG4?

For technical support, including CD74HC73EG4 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your CD74HC73EG4 requirements.

6.How does Aetrix verify that CD74HC73EG4 is sourced from the original manufacturer or authorized distributors?

All CD74HC73EG4 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that CD74HC73EG4 meets industry standards.

7.What is the process for return or replacement of CD74HC73EG4?

All CD74HC73EG4 units undergo pre-shipment inspection (PSI). If there is an issue with CD74HC73EG4, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The CD74HC73EG4 part is unused and in its original packaging.

Return procedure for CD74HC73EG4:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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