My Inquiry
My Account
Texas Instruments CD74HCT125M
- Part No.:
- CD74HCT125M
- Manufacturer:
- Texas Instruments
- Package:
- 14-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
CD74HCT125M.pdf
- Description:
- IC BUF NON-INVERT 5.5V 14SOIC
- Quantity:
- Payment:
- Shipping:
Inventory:1,397
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
CD74HCT125M from Texas Instruments is a quadruple 3-state buffer IC with LSTTL- and CMOS-compatible inputs, operating from 4.5 V to 5.5 V, supporting –55°C to +125°C temperature range, delivering 38 ns max propagation delay at 4.5 V/50 pF, and enabling bus isolation in digital systems.
For engineers reviewing the CD74HCT125M datasheet, CD74HCT125M pinout, CD74HCT125M application, or CD74HCT125M equivalent, this page delivers verified functional identity, SOIC-14 package mapping, 3-state output timing behavior, input voltage thresholds (VIL ≤ 0.8 V, VIH ≥ 2 V), and real-world bus enable use cases - all confirmed from TI's SCHS415A production datasheet.
Technical Context
This device implements four independent non-inverting buffers (Y = A) with active-low 3-state output enables (OE). Each channel operates with TTL-compatible input thresholds and CMOS-level output drive capability, allowing direct interfacing between legacy LSTTL and modern CMOS logic families.
Its 3-state outputs support high-impedance disconnection under control of dedicated OE pins per channel, enabling bidirectional bus management without external direction control. The SOIC-14 package provides thermal resistance RθJA = 138.7°C/W and supports fanout of up to 10 LSTTL loads.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage | 4.5 V to 5.5 V - ensures compatibility with standard 5 V logic rails while tolerating ±5% supply variation. |
| Input Thresholds | VIL(max) = 0.8 V, VIH(min) = 2 V - guarantees reliable recognition of LSTTL logic levels across full temperature range. |
| Propagation Delay | 38 ns max (CL = 50 pF, VCC = 4.5 V) - defines worst-case signal path latency for synchronous bus timing budgets. |
| Output Drive | ±4 mA (VOL ≤ 0.4 V, VOH ≥ 3.7 V at 4.5 V) - sustains valid logic levels driving up to 10 LSTTL loads or light capacitive loads. |
| Operating Temperature | –55°C to +125°C - qualified for extended industrial, automotive under-hood, and military-grade environments. |
| Quiescent Current | ICC = 160 µA max (TA = –55°C to 125°C) - enables low-static-power operation in always-on subsystems. |
| ESD Rating | HBM ±2000 V - meets IEC 61000-4-2 Level 2 requirements for board-level robustness during handling and assembly. |
Pinout & Package
CD74HCT125M is housed in a 14-pin SOIC (D) package measuring 8.65 mm × 6.0 mm (including pins), with body size 8.65 mm × 3.9 mm. Pin 1 is marked with a beveled corner or dot; pin numbering follows standard SOIC top-view convention.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 4, 10, 13 | Channel OE (active-low) | Independent enable control per buffer; pulls output to high-impedance when logic HIGH. |
| 2, 5, 9, 12 | Channel Input A | Non-inverting data input; accepts TTL- or CMOS-level signals with ≤1 µA leakage. |
| 3, 6, 8, 11 | Channel Output Y | 3-state buffered output; drives HIGH/LOW or floats based on corresponding OE state. |
| 7 | GND | Logic and power ground reference; must be low-impedance connection for noise immunity. |
| 14 | VCC | Positive supply rail; requires local 0.1 µF bypass capacitor placed adjacent to pin. |
Key Features
| Feature | Design Value |
|---|---|
| LSTTL- and CMOS-compatible inputs | VIH(min) = 2 V and VIL(max) = 0.8 V ensure interoperability with both legacy bipolar and modern CMOS logic families. |
| Independent 3-state control per channel | Four separate OE pins allow selective bus segment activation without requiring global enable coordination. |
| Low quiescent power consumption | ICC ≤ 160 µA over full temperature range reduces standby current in battery-backed or energy-sensitive systems. |
| Wide temperature operation | –55°C to +125°C rating supports deployment in harsh environments including automotive engine control units and industrial PLCs. |
| Buffered inputs | Reduces capacitive loading on upstream drivers and improves noise immunity compared to unbuffered gate inputs. |
Applications
| Industrial Bus Isolation | Legacy System Interface |
|---|---|
Use Scenario: Isolating microcontroller GPIO banks from shared peripheral buses in programmable logic controllers. IC Role / Device Role / Timing Role: Quad buffer acts as directional gate controller, enabling/disabling data flow per channel using discrete OE signals synchronized to CPU read/write cycles. Use Value: Prevents bus contention during multi-master arbitration and eliminates need for external direction-control logic or transceivers. |
Use Scenario: Interfacing FPGA I/O banks with older 5 V TTL peripherals such as DACs, ADCs, or display drivers. IC Role / Device Role / Timing Role: Level-shifting buffer translates modern CMOS output voltages to LSTTL-compatible thresholds while maintaining fast edge rates. Use Value: Enables direct connection without pull-up resistors or voltage translators, preserving 38 ns timing margin at 4.5 V supply. |
| Test Equipment Signal Routing | Automotive Sensor Multiplexing |
Use Scenario: Selectively routing calibration signals from a central test controller to multiple sensor channels in automated test fixtures. IC Role / Device Role / Timing Role: 3-state outputs isolate unused channels during parallel testing, preventing signal crosstalk and loading effects. Use Value: Maintains signal integrity across 50 pF trace loads and supports repeatable 10 ns transition times per channel. |
Use Scenario: Enabling/disabling analog sensor outputs (e.g., pressure, temperature) before feeding into shared ADC inputs in engine control modules. IC Role / Device Role / Timing Role: Buffer isolates sensors electrically during sleep mode while retaining fast wake-up response via OE assertion. Use Value: Reduces system leakage current by >90% versus permanently connected sensors, meeting ISO 16750-2 cold-cranking requirements. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 3-state buffer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74HCT125DR | Same logic function, identical SOIC-14 footprint, but TI's newer production variant with updated MSL-1 reflow profile and RoHS-compliant NIPDAU/SN finish. | Valid drop-in replacement for new designs; not recommended for legacy repair where CD74HCT125M marking or obsolete status is required. | Select SN74HCT125DR for volume production requiring current TI manufacturing standards and long-term availability. |
| MC74HCT125AD | Onsemi variant with identical electrical specs (VIL/VOL/tpd), but different thermal metrics (RθJA = 125°C/W) and wider lead finish options including matte tin. | Suitable for mixed-source BOMs where second-source qualification is mandated; pinout and timing fully matched. | Choose MC74HCT125AD when dual-sourcing is contractually required or when specific lead-finish compliance (e.g., matte tin) is needed. |
Compared with CD74HCT125M, SN74HCT125DR offers improved manufacturability and lifecycle assurance, while MC74HCT125AD provides certified second-source equivalence with identical functional behavior and SOIC-14 mechanical compatibility - both avoid PCB redesign and preserve timing margins in existing layouts.
Availability
CD74HCT125M is available at Aetrix Electronics and suitable for industrial bus isolation, legacy system interface, test equipment signal routing, and automotive sensor multiplexing requiring stable component supply across extended temperature ranges and long product lifecycles.
Supply support for CD74HCT125M includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a U.S.-based semiconductor company founded in 1930, specializing in analog, embedded processing, and logic solutions with broad industrial and automotive qualification.
CD74HCT125M belongs to TI's HCT (High-Speed CMOS TTL-compatible) logic family, designed specifically for seamless integration between legacy TTL systems and modern CMOS-based controllers in harsh-environment applications.
FAQ
What is the exact package type and dimensions of CD74HCT125M?
CD74HCT125M uses a 14-pin SOIC (D) package with overall dimensions of 8.65 mm × 6.0 mm (including leads) and body size 8.65 mm × 3.9 mm. This matches TI's standard SOIC-D outline drawing SLMA005, and is distinct from PDIP (N) and CDIP (J) variants listed in the same datasheet.
Does CD74HCT125M support true 5 V operation across its full temperature range?
Yes, CD74HCT125M is fully specified for 4.5 V to 5.5 V supply operation across –55°C to +125°C. Electrical characteristics including VOH ≥ 3.7 V, VOL ≤ 0.4 V, and tpd ≤ 38 ns are guaranteed at VCC = 4.5 V and TA = –55°C to 125°C per Section 5.5 and 5.6 of the SCHS415A datasheet.
How does the 3-state functionality work on CD74HCT125M?
Each of the four buffers in CD74HCT125M has a dedicated active-low output enable (OE) pin. When OE is LOW, the corresponding Y output follows the A input (Y = A); when OE is HIGH, the Y output enters high-impedance state (Z), drawing only ±10 µA leakage (IOZ) as specified in Section 5.5.
Can CD74HCT125M drive a 50 pF load while maintaining timing specifications?
Yes - CD74HCT125M's switching characteristics are explicitly tested and guaranteed at CL = 50 pF. Propagation delay (tpd) is 38 ns max, enable delay (ten) is 38 ns max, and disable delay (tdis) is 42 ns max under those conditions at VCC = 4.5 V and TA = –55°C to 125°C (Section 5.6).
Is CD74HCT125M still in active production or obsolete?
Per TI's official PACKAGE OPTION ADDENDUM (15-Jul-2026), CD74HCT125M is marked "Obsolete" with no active orderable quantity, while CD74HCT125M96E4.A remains Active with 2500-piece tape-and-reel packaging and Level-1 MSL rating - confirming CD74HCT125M96E4.A as the current production version of this SOIC-14 device.
CD74HCT125M Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- 74HCT
- Package/Case:
- 14-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Logic Type:
- Buffer, Non-Inverting
- Number of Elements:
- 4
- Number of Bits per Element:
- 1
- Input Type:
- -
- Output Type:
- 3-State
- Current - Output High, Low:
- 6mA, 6mA
- Voltage - Supply:
- 4.5V ~ 5.5V
- Operating Temperature:
- -55°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 14-SOIC
CD74HCT125M FAQ
1.How can I place an order for CD74HCT125M through Aetrix?
Please submit a Request for Quotation (RFQ) for CD74HCT125M on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for CD74HCT125M reliable?
The price and inventory of CD74HCT125M are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for CD74HCT125M is usually 5 days.
3.What payment methods are accepted for CD74HCT125M?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for CD74HCT125M transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for CD74HCT125M?
CD74HCT125M orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your CD74HCT125M order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for CD74HCT125M?
For technical support, including CD74HCT125M datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your CD74HCT125M requirements.
6.How does Aetrix verify that CD74HCT125M is sourced from the original manufacturer or authorized distributors?
All CD74HCT125M products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that CD74HCT125M meets industry standards.
7.What is the process for return or replacement of CD74HCT125M?
All CD74HCT125M units undergo pre-shipment inspection (PSI). If there is an issue with CD74HCT125M, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The CD74HCT125M part is unused and in its original packaging.
Return procedure for CD74HCT125M:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
CD74HCT125M Tags
-
SN74LVC1G17DBVR
Texas Instruments
-
SN74LVC1G07DCKR
Texas Instruments
-
SN74LVC1G17DCKR
Texas Instruments
-
SN74LVC1G07DBVR
Texas Instruments
-
SN74LVC1G125DCKR
Texas Instruments
-
SN74AHCT1G126DBVR
Texas Instruments
-
SN74LVC1G125DBVR
Texas Instruments
-
SN74AHCT1G125DBVR
Texas Instruments
-
SN74LVC2G17DBVR
Texas Instruments
-
SN74LVC2G07DCKR
Texas Instruments
-
SN74LVC1G34DCKR
Texas Instruments
-
SN74LVC2G17DCKR
Texas Instruments
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
