Texas Instruments CD74HCT367MT
- Part No.:
- CD74HCT367MT
- Manufacturer:
- Texas Instruments
- Package:
- 16-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
CD74HCT367MT.pdf
- Description:
- IC BUF NON-INVERT 5.5V 16SOIC
- Quantity:
- Payment:

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Inventory:735
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Product details
Overview
CD74HCT367MT from Texas Instruments is a high-speed CMOS hex non-inverting buffer/line driver with three-state outputs, designed for bus interface and data routing in industrial control and instrumentation systems. It features dual independent 3-state enables (1OE, 2OE), 4-channel + 2-channel output grouping, 4.5 V to 5.5 V operation, and typical propagation delay of 9 ns at VCC = 5 V, CL = 15 pF.
For engineers reviewing the CD74HCT367MT datasheet, CD74HCT367MT pinout, CD74HCT367MT application, or CD74HCT367MT equivalent, this page delivers verified functional identity, validated SOIC-16 pin mapping, confirmed HCT-family LSTTL-compatible input thresholds, and real-world bus-driving performance metrics - all critical for signal integrity validation and legacy TTL interface replacement.
Technical Context
The CD74HCT367MT implements six independent non-inverting buffers, partitioned into two electrically isolated groups: four buffers controlled by 1OE (pins 1, 1A1–1A4, 1Y1–1Y4) and two by 2OE (pins 15, 2A1–2A2, 2Y1–2Y2). Each output drives up to 15 LSTTL loads with ±4 mA output current capability at VOH/VOL specifications.
Its HCT logic family ensures direct compatibility with LS-TTL inputs (VIL ≤ 0.8 V, VIH ≥ 2.0 V), while maintaining CMOS-level input leakage (≤1 μA) and low ICC (≤160 μA over full temperature range). Propagation delay symmetry (tPLH ≈ tPHL) and balanced transition times support clean edge timing in synchronous bus environments.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Logic Family | HCT - compatible with LS-TTL input voltage levels and drive strength, enabling drop-in replacement in legacy 5 V TTL systems |
| Supply Voltage | 4.5 V to 5.5 V - operates reliably across standard 5 V rail tolerances without level-shifting |
| Propagation Delay | 9 ns typical (VCC = 5 V, CL = 15 pF) - supports >30 MHz bus toggle rates with margin for trace delays |
| Output Drive | ±4 mA at VOH/VOL - sufficient to drive 15 LSTTL inputs or 50 pF bus capacitance with <38 ns max enable/disable delay |
| Operating Temperature | –55 °C to +125 °C - qualified for extended industrial and aerospace environments without derating |
| Input Leakage | ≤1 μA at VI = VCC or GND - negligible loading on upstream drivers, preserving fanout integrity |
| Three-State Leakage | ±10 μA max (VO = VCC or GND) - ensures high-impedance isolation meets bus contention safety requirements |
Pinout & Package
CD74HCT367MT is supplied in a 16-pin SOIC (D) package with nominal body size 9.90 mm × 3.90 mm, RoHS-compliant NiPdAu lead finish, and moisture sensitivity level (MSL) Level-1 (unlimited floor life at ≤30 °C/60% RH).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (1OE) | Group 1 Output Enable | Active-low control for Y1–Y4 outputs; asserts high-impedance state when high |
| 2–7, 9–10 (1A1–1A4, 1Y1–1Y4) | Group 1 Data Inputs / Non-Inverting Outputs | Four matched input-output pairs; Yn = An when 1OE = low |
| 15 (2OE) | Group 2 Output Enable | Active-low control for Y1–Y2 of second group; independent of 1OE |
| 12–14 (2A1–2A2, 2Y1–2Y2) | Group 2 Data Inputs / Non-Inverting Outputs | Two additional buffered channels; enables partial bus gating without affecting Group 1 |
| 8 (GND) | Ground Reference | Primary return path for all I/O and supply currents; must be low-impedance |
| 16 (VCC) | Positive Supply | 5 V ±5% power rail; requires local 0.1 μF ceramic bypass capacitor per device |
Key Features
| Feature | Design Value |
|---|---|
| Dual independent 3-state enables | Allows selective activation of 4-channel (1OE) and 2-channel (2OE) groups - essential for hierarchical bus arbitration and partial subsystem isolation |
| LSTTL input compatibility | VIL ≤ 0.8 V and VIH ≥ 2.0 V at VCC = 4.5–5.5 V - eliminates need for external level shifters when interfacing with legacy 5 V TTL logic |
| High-current bus driver outputs | ±4 mA drive strength per output - sustains signal integrity driving long traces, multiple receivers, or capacitive loads up to 50 pF |
| Low power CMOS core | ICC ≤ 160 μA over –55 °C to +125 °C - reduces thermal load and system-level power budget vs. equivalent LS-TTL devices |
| Wide temperature operation | Rated from –55 °C to +125 °C - supports deployment in uncontrolled industrial enclosures, automotive under-hood, and military platforms |
Applications
| Industrial PLC Backplane Interface | Test Equipment Signal Routing |
|---|---|
|
Use Scenario: Isolating and buffering address/data lines between microcontroller and modular I/O cards in a programmable logic controller rack. IC Role / Device Role / Timing Role: Hex non-inverting buffer providing direction-controlled bus access via dual OE signals, enabling time-multiplexed card addressing without contention. Use Value: Dual OE architecture allows independent gating of 4-bit address lanes and 2-bit control/status lines - reducing PCB routing complexity and eliminating external logic for bus arbitration. |
Use Scenario: Switching measurement signals between DUT ports and instrument front-ends in automated test equipment (ATE) racks. IC Role / Device Role / Timing Role: Three-state line driver managing bidirectional analog/digital signal paths with precise enable timing to prevent signal collisions during reconfiguration. Use Value: 9 ns propagation delay and <38 ns enable/disable latency ensure sub-25 ns switching windows - meeting tight timing budgets for high-speed parametric testing. |
| Military Avionics Data Bus | Legacy System Upgrade Module |
|
Use Scenario: Interfacing modern FPGA-based processing modules with legacy MIL-STD-1553 or ARINC 429 transceivers in airborne mission computers. IC Role / Device Role / Timing Role: Level-translating and bus-driving buffer ensuring LS-TTL-compatible signaling margins across wide temperature and vibration conditions. Use Value: –55 °C to +125 °C rating and ±4 mA drive guarantee reliable operation in sealed avionics enclosures without forced cooling or derating. |
Use Scenario: Replacing obsolete SN74LS367 in aging industrial controllers where board space and pinout must be preserved. IC Role / Device Role / Timing Role: Pin-compatible HCT upgrade delivering identical SOIC-16 footprint, same pin functions, and improved noise immunity and power efficiency. Use Value: Direct drop-in replacement with 30% lower ICC and 3× higher noise immunity (NIL/NIH = 30% of VCC) - extending system uptime and reducing field failures. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar hex non-inverting three-state buffer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74HCT367N | Same HCT logic family, identical pinout and DC specs; differs only in PDIP-16 packaging (vs. SOIC-16) and wider body (19.31 mm × 6.35 mm) | Preferred for through-hole prototyping or legacy wave-soldered assemblies; lacks SOIC thermal and density advantages | Select SN74HCT367N only when PDIP mounting is required; otherwise CD74HCT367MT offers superior board area efficiency and reflow compatibility |
| CD74HCT367M96 | Functionally identical, same SOIC-16 package, but supplied in 2500-unit tape-and-reel format (vs. tube); active status vs. CD74HCT367MT's obsolete status | Designed for high-volume SMT production; supports automated pick-and-place with Q1 pin-1 orientation | CD74HCT367M96 is the recommended production-grade variant; CD74HCT367MT is obsolete and not recommended for new designs |
Compared with SN74HCT367N and CD74HCT367M96, CD74HCT367MT shares identical electrical behavior and pin mapping but is obsolete - its SOIC-16 form factor matches CD74HCT367M96, while SN74HCT367N serves through-hole use cases requiring different mechanical integration.
Availability
CD74HCT367MT is available at Aetrix Electronics and suitable for industrial control backplanes, automated test equipment signal routing, military avionics interfaces, and legacy system upgrades requiring stable component supply and long-term sourcing continuity.
Supply support for CD74HCT367MT includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and logic solutions, with decades of heritage in high-reliability logic families.
The CD74HCT367MT belongs to TI's CD74HCT high-speed CMOS logic portfolio, engineered for seamless interoperability with legacy TTL systems while delivering CMOS power efficiency and extended temperature resilience.
FAQ
Is CD74HCT367MT pin-compatible with SN74LS367?
Yes, CD74HCT367MT is pin-compatible with SN74LS367 and functionally equivalent as a hex non-inverting three-state buffer. Its HCT inputs meet LS-TTL voltage thresholds (VIL ≤ 0.8 V, VIH ≥ 2.0 V), and outputs drive the same 15 LSTTL loads. However, CD74HCT367MT operates only from 4.5 V to 5.5 V and draws significantly less supply current - making it a direct, low-power drop-in replacement in existing 5 V designs.
What is the maximum bus capacitance CD74HCT367MT can drive reliably?
CD74HCT367MT can reliably drive up to 50 pF of total bus capacitance while maintaining specified timing: propagation delay remains ≤38 ns and output transition time ≤18 ns at VCC = 5 V, CL = 50 pF. This capacity supports typical backplane traces and 5–8 downstream receivers. For heavier loads, parallel outputs or dedicated bus transceivers are recommended.
Does CD74HCT367MT support mixed-voltage interfacing (e.g., 3.3 V logic inputs)?
No - CD74HCT367MT is an HCT-family device optimized for 5 V operation and LS-TTL compatibility. Its input thresholds are fixed relative to VCC (VIL ≤ 0.8 V, VIH ≥ 2.0 V), so 3.3 V logic signals may not register reliably as HIGH. For mixed-voltage systems, use a true dual-supply translator or a 74LVC-series buffer instead of CD74HCT367MT.
Why is CD74HCT367MT marked as obsolete, and what should I use instead?
CD74HCT367MT is obsolete per Texas Instruments' packaging roadmap; its SOIC-16 variant has been superseded by CD74HCT367M96 (same package, tape-and-reel format, active status). CD74HCT367M96 offers identical electrical and mechanical specs, full production support, and automated assembly compatibility - making it the recommended replacement for all new and ongoing CD74HCT367MT designs.
How does the dual OE architecture of CD74HCT367MT improve system design?
The dual OE structure (1OE for four outputs, 2OE for two) in CD74HCT367MT enables granular bus control - for example, using 1OE to gate a 4-bit address bus while keeping 2OE-enabled status lines always active. This eliminates external gating logic, reduces PCB layer count, and simplifies timing analysis since each group's enable path is independent and electrically isolated within the die.
CD74HCT367MT Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- 74HCT
- Package/Case:
- 16-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Logic Type:
- Buffer, Non-Inverting
- Number of Elements:
- 2
- Number of Bits per Element:
- 2, 4 (Hex)
- Input Type:
- -
- Output Type:
- 3-State
- Current - Output High, Low:
- 4mA, 4mA
- Voltage - Supply:
- 4.5V ~ 5.5V
- Operating Temperature:
- -55°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-SOIC
CD74HCT367MT FAQ
1.How can I place an order for CD74HCT367MT through Aetrix?
Please submit a Request for Quotation (RFQ) for CD74HCT367MT on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for CD74HCT367MT reliable?
The price and inventory of CD74HCT367MT are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for CD74HCT367MT is usually 5 days.
3.What payment methods are accepted for CD74HCT367MT?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for CD74HCT367MT transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for CD74HCT367MT?
CD74HCT367MT orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your CD74HCT367MT order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for CD74HCT367MT?
For technical support, including CD74HCT367MT datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your CD74HCT367MT requirements.
6.How does Aetrix verify that CD74HCT367MT is sourced from the original manufacturer or authorized distributors?
All CD74HCT367MT products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that CD74HCT367MT meets industry standards.
7.What is the process for return or replacement of CD74HCT367MT?
All CD74HCT367MT units undergo pre-shipment inspection (PSI). If there is an issue with CD74HCT367MT, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The CD74HCT367MT part is unused and in its original packaging.
Return procedure for CD74HCT367MT:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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