Texas Instruments CDCE706PWR

Overview

CDCE706PWR from Texas Instruments is a programmable 3-PLL clock synthesizer/multiplier/divider in a 20-pin TSSOP package, supporting crystal (8–54 MHz), LVCMOS, or differential inputs up to 200 MHz, and delivering six LVCMOS outputs up to 300 MHz with ≤60 ps typical cycle-to-cycle jitter. It enables zero-ppm output clock generation via independent M/N/P divider programming and integrated loop filters, used in high-speed serial interface timing for telecom and datacom systems.

For engineers reviewing the CDCE706PWR datasheet, CDCE706PWR pinout, CDCE706PWR application, or CDCE706PWR equivalent, key selection criteria include its triple-PLL architecture with SSC support on PLL2, EEPROM-based nonvolatile configuration, SMBus programmability, dual-output supply rails (VCCOUT1/VCCOUT2), and 7-bit post-divider per output for fine-grained frequency synthesis.

Technical Context

The CDCE706PWR integrates three independent PLLs-PLL1, PLL2 (with center/down-spread-spectrum clocking), and PLL3-each configurable with 9-bit reference dividers (M = 1–511) and 12-bit feedback dividers (N = 1–4095), enabling precise VCO frequencies from 80 MHz to 300 MHz. Its programmable 6×6 output switching matrix routes any PLL output to any of six Y0–Y5 pins, each with a dedicated 7-bit post-divider (1–127) and invert logic.

Input selection is flexible: CLK_IN0 accepts crystal, single-ended LVCMOS, or positive differential signals; CLK_IN1 serves as crystal output, second LVCMOS input, or negative differential input. Control inputs S0/S1 support dynamic mode selection (e.g., PLL bypass, output enable/disable, power-down), while SMBus interface (SCLOCK/SDATA) enables in-circuit EEPROM programming without high-voltage programming.

Key Specifications

Pinout & Package

CDCE706PWR is packaged in a 20-pin TSSOP (PW) package with exposed pad, thermal resistance θ_JA = 51.9°C/W at 500 LFM airflow. Pin functions are validated per TI SCAS815I datasheet Rev. November 2008.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar clock synthesizer applications.

Compared with CDCE706PWR, CDCE906PWR offers superior jitter and higher frequency headroom but demands more complex power design, while ICS843002AGLFT simplifies BOM with fixed configuration yet sacrifices field programmability and EMI mitigation features.

Availability

CDCE706PWR is available at Aetrix Electronics and suitable for PCIe Gen2 clock distribution, SATA host controller timing, Gigabit Ethernet PHY synchronization, and industrial FPGA clock tree applications requiring stable component supply across extended product lifecycles.

Supply support for CDCE706PWR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and clock solutions, with decades of expertise in precision timing and signal integrity.

The CDCE706PWR belongs to TI's CDCE clock synthesizer family, designed specifically for high-flexibility, low-jitter clock generation in space-constrained telecom, datacom, and industrial systems requiring multi-protocol timing consolidation.

FAQ

What input clock sources does the CDCE706PWR support?

The CDCE706PWR supports three input types: an 8–54 MHz fundamental-mode crystal connected to CLK_IN0/CLK_IN1, single-ended LVCMOS signals up to 200 MHz on either input, or differential clock inputs (LVDS/LVPECL-compatible via internal termination) up to 200 MHz. Input selection is configured via SMBus registers, and the device automatically adapts biasing and termination based on the chosen mode.

How is the CDCE706PWR programmed, and does it retain settings after power loss?

The CDCE706PWR is programmed via its SMBus interface (SCLOCK/SDATA pins) using byte-write or block-write commands. All configuration registers-including PLL dividers, output routing, slew rate, and inversion-are stored in on-chip nonvolatile EEPROM, which retains settings indefinitely after power removal. The device boots with factory-default values if EEPROM is unprogrammed.

Can the CDCE706PWR generate zero-ppm output frequencies from a 27 MHz crystal?

Yes. Using a 27 MHz crystal, the CDCE706PWR achieves zero-ppm accuracy by selecting integer M/N divider ratios-for example, M = 1 and N = 6 yields exactly 162 MHz (27 × 6). The 9-bit M-divider (1–511) and 12-bit N-divider (1–4095) provide sufficient resolution to match common protocol frequencies like 100 MHz, 125 MHz, and 156.25 MHz without fractional error.

Does the CDCE706PWR support spread-spectrum clocking (SSC), and on which outputs?

SSC is supported exclusively on PLL2 and can be routed to any output (Y0–Y5) via the 6×6 switching matrix. PLL2 offers both center-spread and down-spread modes with programmable modulation frequency and depth. PLL1 and PLL3 do not support SSC, preserving deterministic jitter performance for critical timing paths.

What are the power supply requirements for the CDCE706PWR's outputs?

The CDCE706PWR uses three independent supply pins: VCC (3.0–3.6 V) powers core logic and PLLs; VCCOUT1 (2.3–3.6 V) powers Y0/Y1; VCCOUT2 (2.3–3.6 V) powers Y2–Y5. This separation allows mixed-voltage operation-e.g., Y0/Y1 at 2.5 V for legacy interfaces and Y2–Y5 at 3.3 V for modern FPGAs-without level shifters.