Texas Instruments CDCE906PW

Overview

CDCE906PW from Texas Instruments is a programmable 3-PLL clock synthesizer/multiplier/divider in a 20-pin TSSOP package, supporting up to 167 MHz LVCMOS outputs, 3.3-V operation, and integrated spread-spectrum clocking (SSC) for EMI reduction. It generates precise video (27/54 MHz) and audio system clocks from sampling frequencies including 44.1 kHz and 48 kHz.

For engineers reviewing the CDCE906PW datasheet, CDCE906PW pinout, CDCE906PW application, or CDCE906PW equivalent, key selection considerations include its triple-PLL architecture with independent M/N/P dividers, EEPROM-programmable output slew-rate control, SMBus-based in-circuit configuration, and dual VCCOUT supplies enabling mixed-voltage output operation (2.3–3.6 V).

Technical Context

The CDCE906PW integrates three fully independent PLLs-PLL1, PLL2 (with SSC support), and PLL3-each configurable with 9-bit reference divider (M = 1–511) and 12-bit feedback divider (N = 1–4095), enabling zero-ppm output clock generation from input references as low as 8 MHz. Its 6×6 programmable output switching matrix routes any PLL's VCO signal to any of six outputs.

Each output features a 7-bit post-divider (1–127), programmable inversion, and four slew-rate settings (tr/tf down to 0.4 ns at 3.3 V). Internal loop filter components auto-adjust per PLL configuration to optimize jitter transfer and stability, while EEPROM stores user-defined settings without external high-voltage programming.

Key Specifications

Pinout & Package

Package: TSSOP-20 (PW), 0.65 mm pitch, 6.6 mm × 6.6 mm footprint, surface-mount compatible.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar clock synthesizer applications.

Compared with CDCE906PW, CDCE925PW offers higher output speed but sacrifices SSC, EEPROM, and multi-PLL flexibility; Si5338A-D-GM delivers superior jitter and protocol support but increases system complexity and cost - CDCE906PW remains optimal for balanced cost, integration, and EMI-conscious consumer/industrial clocking.

Availability

CDCE906PW is available at Aetrix Electronics and suitable for audio system clocking, video timing reference, industrial PLC backplane synchronization, and embedded communication processor clocking requiring stable component supply and long-term manufacturability.

Supply support for CDCE906PW includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and clock solutions, with decades of expertise in high-precision timing ICs for industrial, automotive, and consumer markets.

The CDCE906PW belongs to TI's Pro-Clock™ family of programmable clock synthesizers, designed specifically for cost-sensitive, space-constrained applications requiring flexible multi-frequency clock generation with integrated EMI mitigation.

FAQ

What is the maximum crystal frequency supported by the CDCE906PW?

The CDCE906PW supports crystal input frequencies from 8 MHz to 54 MHz in fundamental mode. Operation above 50 MHz requires crystal effective series resistance (ESR) ≤50 Ω to ensure stable startup. The device also accepts LVCMOS or differential clock inputs up to 167 MHz, making it compatible with both discrete crystals and buffered oscillator modules.

Does the CDCE906PW require external loop filter components?

No, the CDCE906PW integrates all required loop filter components internally. Its PLLs automatically configure internal resistors and capacitors based on selected M/N divider values and VCO frequency mode (normal or high-speed), eliminating external passive components and reducing PCB area and bill-of-materials cost.

Can the CDCE906PW generate different output frequencies simultaneously?

Yes, the CDCE906PW can generate six independent output frequencies simultaneously using its 3-PLL architecture and 6×6 programmable switching matrix. Each output (Y0–Y5) can be assigned any PLL's VCO signal and further divided by a unique 7-bit post-divider (1–127), enabling true multi-frequency synthesis from a single reference.

How is the CDCE906PW programmed, and does it retain settings after power loss?

The CDCE906PW is programmed via its SMBus 2.0 interface using Byte Write or Block Write commands. All register settings-including PLL dividers, output configurations, and SSC parameters-are stored in on-chip EEPROM, retaining user-defined configurations across power cycles without external memory or boot-time reprogramming.

What are the power supply requirements for the CDCE906PW outputs?

The CDCE906PW uses three power domains: VCC (3.0–3.6 V) powers core logic and PLLs; VCCOUT1 (2.3–3.6 V) supplies Y0 and Y1; VCCOUT2 (2.3–3.6 V) supplies Y2–Y5. This dual-output-rail architecture allows mixed-voltage signaling-for example, 3.3 V for MCU clocks and 2.5 V for PHY clocks-without external level shifters.