Texas Instruments CDCE906PWR

Overview

CDCE906PWR from Texas Instruments is a programmable 3-PLL clock synthesizer/multiplier/divider in TSSOP-20 package, supporting up to 167 MHz LVCMOS outputs, 3.3-V operation, and integrated EEPROM for in-system configuration. It delivers zero-ppm output clocks from crystal or LVCMOS/differential inputs (8–54 MHz crystal, up to 167 MHz clock input) and enables spread-spectrum clocking (SSC) on PLL2 for EMI reduction - used in digital audio/video timing systems requiring precise multi-frequency synthesis.

For engineers reviewing the CDCE906PWR datasheet, CDCE906PWR pinout, CDCE906PWR application, or CDCE906PWR equivalent, key selection criteria include its 3 independent PLLs with wide M/N divider ranges (M=1–511, N=1–4095), 6-programmable LVCMOS outputs with slew-rate control and 7-bit post-dividers, SSC modulation options (±0.1% to ±0.4% center-spread, 1–3% down-spread), and SMBus-based EEPROM programming without high-voltage requirements.

Technical Context

The CDCE906PWR integrates three fully independent PLLs - PLL1, PLL2 (with SSC capability), and PLL3 - each configurable with 9-bit reference dividers (M) and 12-bit feedback dividers (N), enabling precise VCO frequency synthesis from 80 MHz to 300 MHz (normal or high-speed mode). Its 6×6 output switching matrix routes any PLL or bypassed input to any of six LVCMOS outputs, each with programmable 7-bit post-divider (1–127), polarity inversion, and four slew-rate settings.

Input flexibility includes crystal (8–54 MHz), single-ended LVCMOS, or differential clock signals; dual input pins (CLK_IN0/CLK_IN1) support crystal oscillator mode or differential pair reception. Power architecture separates VCC (3.3 V core) from VCCOUT1 (Y0/Y1) and VCCOUT2 (Y2–Y5), allowing 2.3–3.6 V output supply voltages with corresponding drive-current scaling.

Key Specifications

Pinout & Package

TSSOP-20 package (PW), 0.65 mm pitch, 6.6 mm × 6.6 mm footprint; thermally optimized with θ_JA = 51.9°C/W at 500 LFM airflow.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar clock synthesizer applications.

Compared with CDCE925PWR and ICS9FGP108A, the CDCE906PWR uniquely balances compact TSSOP-20 packaging, on-chip loop filters, EEPROM programmability, and SSC support - making it optimal for cost-sensitive, space-constrained embedded systems needing EMI-compliant multi-frequency synthesis.

Availability

CDCE906PWR is available at Aetrix Electronics and suitable for digital audio timing, video display synchronization, industrial PLC backplanes, and embedded communication processor clocking requiring stable component supply and long-term manufacturability.

Supply support for CDCE906PWR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and clock solutions, with decades of expertise in precision timing ICs and high-reliability manufacturing.

The CDCE906PWR belongs to TI's Pro-Clock™ family of programmable clock synthesizers, designed specifically for consumer, industrial, and communications equipment requiring flexible, low-EMI, multi-output clock generation in minimal footprint.

FAQ

What is the maximum input frequency supported by CDCE906PWR?

The CDCE906PWR accepts LVCMOS or differential clock inputs up to 167 MHz in PLL mode, and crystal inputs from 8 MHz to 54 MHz. Input frequency limits are enforced by internal circuitry and must remain within recommended operating conditions to ensure stable PLL lock and low jitter performance. Exceeding 167 MHz may cause functional failure or degraded timing margins.

Does CDCE906PWR support spread-spectrum clocking on all three PLLs?

No - spread-spectrum clocking (SSC) is supported only on PLL2 of the CDCE906PWR. PLL1 and PLL3 operate in fixed-frequency mode. The SSC feature offers center-spread (±0.1%, ±0.25%, ±0.4%) and down-spread (1%, 1.5%, 2%, 3%) modulation to reduce electromagnetic interference, making CDCE906PWR suitable for EMI-sensitive video and audio applications.

How is the CDCE906PWR configured after power-up?

The CDCE906PWR boots with a factory-default EEPROM configuration that enables all six outputs at 27 MHz (derived from a 27 MHz crystal input), with PLL1, PLL2, and PLL3 active and SSC disabled. This default state allows immediate operation without prior programming. Custom configurations can be written via SMBus and retained in non-volatile memory for subsequent power cycles.

Can CDCE906PWR generate zero-ppm output clocks from non-standard crystal frequencies?

Yes - the CDCE906PWR achieves zero-ppm output accuracy using its wide M/N divider ranges (M = 1–511, N = 1–4095), allowing exact integer ratios between input and desired output frequencies. For example, a 24.576 MHz audio clock can be generated precisely from a 12.288 MHz crystal using M=1, N=2, eliminating accumulated timing drift in synchronous digital audio systems.

What are the power supply requirements for CDCE906PWR outputs Y0–Y5?

CDCE906PWR uses separate output power rails: VCCOUT1 (pin 14) powers Y0 and Y1 (2.3–3.6 V), while VCCOUT2 (pin 18) powers Y2–Y5 (2.3–3.6 V). Output drive strength scales with supply voltage - at 2.5 V, max output current is ±4 mA; at 3.3 V, it is ±6 mA. This separation enables mixed-voltage system interfacing and optimized power delivery per output group.