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Texas Instruments CDCEL913PWR
- Part No.:
- CDCEL913PWR
- Manufacturer:
- Texas Instruments
- Package:
- 14-TSSOP (0.173", 4.40mm Width)
- Datasheet:
-
CDCEL913PWR.pdf
- Description:
- IC PLL CLOCK SYNTHESIZER 14TSSOP
- Quantity:
- Payment:
- Shipping:
Inventory:995
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Product details
Overview
CDCEL913PWR from Texas Instruments is a 1-PLL, 3-output programmable LVCMOS clock generator with spread-spectrum clocking (SSC) for EMI reduction, 1.8-V core supply, 1.8-V output supply, and 230-MHz maximum output frequency. It supports crystal (8–32 MHz) or LVCMOS input, integrates PLL loop filter components, and delivers typical 80-ps cycle-to-cycle jitter at 1.8-V VDDOUT.
For engineers reviewing the CDCEL913PWR datasheet, CDCEL913PWR pinout, CDCEL913PWR application, or CDCEL913PWR equivalent, this device serves as a low-power, in-system programmable timing solution for video/audio interfaces, USB/Bluetooth/WLAN systems, and TI DaVinci/OMAP platforms requiring precise zero-ppm clock synthesis and EMI-compliant SSC modulation.
Technical Context
The CDCEL913PWR implements a single high-stability PLL with integrated loop filter components and programmable M/N dividers to generate three independent LVCMOS outputs up to 230 MHz from one input source. Its VCXO mode enables ±120–±150 ppm frequency pulling via analog control voltage (VCtrl), supporting synchronization to external PWM signals.
It uses a 2-wire I²C-compatible SDA/SCL interface (up to 400 kHz) for volatile register and nonvolatile EEPROM programming, with dual-function S1/SDA and S2/SCL pins configurable via EEPROM. Three dedicated control inputs (S0/S1/S2) support real-time frequency switching, SSC selection, and output enable/power-down without reprogramming.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output count | 3 independent LVCMOS outputs (Y1/Y2/Y3), each programmable to any frequency ≤230 MHz |
| Input support | External crystal (8–32 MHz) or single-ended LVCMOS clock (≤160 MHz); on-chip VCXO with ±120–±150 ppm pull range |
| Supply voltages | 1.8-V core (VDD); 1.8-V output supply (VDDOUT) - fixed for CDCEL913, unlike CDCE913's 2.5/3.3-V option |
| Jitter performance | Typical 80-ps cycle-to-cycle jitter and 100-ps peak-to-peak period jitter at 1.8-V VDDOUT, fOUT = 50 MHz |
| SSC capability | Programmable center-spread or down-spread modulation (0–±2.0%) to reduce EMI in dense PCB layouts |
| Programming interface | 2-wire serial (SDA/SCL), I²C/SMBus compatible, up to 400 kHz; EEPROM stores factory-default or custom configurations |
| Operating range | –40°C to +85°C ambient temperature; 1.7–1.9 V VDD; 1.7–1.9 V VDDOUT |
Pinout & Package
Packaged in 14-pin TSSOP (PW), 5 mm × 6.4 mm footprint, with exposed pad not electrically connected. Pinout optimized for noise isolation: separate VDD (pin 3) and dual VDDOUT (pins 6, 7) supply rails; dedicated ground pins (5, 10); and LVCMOS outputs Y1 (11), Y2 (9), Y3 (8) placed adjacent to minimize skew.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| Xin/CLK (1) | Clock input | Accepts crystal (fundamental mode) or LVCMOS signal; internal load capacitance programmable 0–20 pF |
| S0 (2) | User control input | Dedicated LVCMOS input (500-kΩ pullup); selects frequency/SSC/output state per EEPROM-defined mapping |
| VDD (3) | Core power supply | 1.8-V nominal supply for PLL, logic, and registers; must be decoupled near pin |
| VCtrl (4) | VCXO control voltage | Analog input (0–1.8 V) enabling ±120–±150 ppm frequency pulling; leave open or pull up if unused |
| GND (5, 10) | Ground reference | Two dedicated ground pins for separating analog/digital return paths and minimizing noise coupling |
| VDDOUT (6, 7) | Output power supply | 1.8-V rail powering all three LVCMOS outputs; requires local 1-µF ceramic decoupling per pin |
| Y1 (11), Y2 (9), Y3 (8) | LVCMOS clock outputs | Three fully independent outputs; each supports 45–55% duty cycle, <0.7 ns rise/fall time (20–80%), and 50-ps output skew (Y1–Y3 @50 MHz) |
| SCL/S2 (12), SDA/S1 (13) | Dual-function I/O | Default: I²C clock/data (SCL/SDA); reconfigurable to control inputs S2/S1 via EEPROM bit [6] of byte 02h |
| Xout (14) | Crystal oscillator output | Drives external crystal; leave open or pull up to VDD if not used; no internal driver when CLK input selected |
Key Features
| Feature | Design Value |
|---|---|
| In-system programmability | Volatile register updates and nonvolatile EEPROM storage (100–1000 write cycles, 10-year retention) enable field reconfiguration without hardware change |
| Zero-ppm clock generation | Deep M/N divider ratios allow exact synthesis of standard audio/video/networking clocks (e.g., 27 MHz → 13.5/24.576/48/125 MHz) from common crystals |
| EMI-reduction SSC | Configurable center/down-spread modulation (0–±2.0%) reduces peak radiated emissions without affecting system timing margins |
| Flexible control interface | Three user-definable inputs (S0/S1/S2) support real-time switching between two preprogrammed frequencies, SSC modes, or output states (active/3-state/power-down) |
| Low-noise PLL architecture | Integrated loop filter components and optimized charge pump deliver 80-ps typical cycle-to-cycle jitter at 1.8-V operation |
Applications
| Digital Television (D-TV) | USB 2.0 Host Controller |
|---|---|
Use Scenario: Generating synchronized pixel, audio, and HDMI TMDS clocks from a single 27-MHz crystal in flat-panel display subsystems. IC Role / Device Role / Timing Role: Primary clock synthesizer providing three phase-aligned LVCMOS clocks (e.g., 148.5 MHz, 27 MHz, 12.288 MHz) with <50-ps inter-output skew. Use Value: Eliminates multiple discrete oscillators, reduces BOM cost and board area, and ensures deterministic jitter alignment across video/audio domains. | Use Scenario: Delivering precise 48-MHz USB PHY clock and 12-MHz USB suspend/resume clock in embedded host controllers. IC Role / Device Role / Timing Role: Single-chip clock source meeting USB 2.0 full-speed timing tolerance (±0.25% accuracy) with SSC enabled for FCC Class B compliance. Use Value: Achieves zero-ppm error relative to 27-MHz reference via integer M/N division, avoiding drift-induced packet retries or enumeration failures. |
| Wi-Fi/BT Combo Module | DaVinci™ Video Processor |
Use Scenario: Supplying 26-MHz WLAN MAC clock, 26-MHz Bluetooth radio clock, and 32.768-kHz RTC clock from one crystal in space-constrained IoT modules. IC Role / Device Role / Timing Role: Multi-frequency clock generator with independent output enables, allowing dynamic power gating of unused domains. Use Value: Reduces crystal count by 2×, lowers EMI through coordinated SSC modulation across both radios, and simplifies layout with single 1.8-V supply domain. | Use Scenario: Providing core processor clock (297 MHz), DDR2 memory clock (148.5 MHz), and video encoder clock (148.5 MHz) in TI DaVinci-based DVR platforms. IC Role / Device Role / Timing Role: High-accuracy clock synthesizer with programmable PLL bypass mode for debug and low-jitter operation during video capture. Use Value: Enables deterministic timing closure across high-speed parallel buses while maintaining <100-ps period jitter for clean video sampling. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar programmable clock generator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| CDCE913PWR | 1.8-V VDDOUT only; 3-output; SSC enabled; TSSOP-14 | Optimized for ultra-low-voltage digital SoC interfaces (e.g., DaVinci, OMAP) | Select for 1.8-V systems requiring minimal power and EMI control |
| CDCE925PWR | 2-PLL, 5-output; same 1.8-V VDDOUT; higher integration but larger TSSOP-20 package | Needed when >3 independent clocks or dual-domain frequency synthesis (e.g., video + audio + network) is required | Choose when additional outputs or independent PLL control justifies extra pins and layout area |
Compared with CDCE913PWR and CDCE925PWR, the CDCEL913PWR provides identical 1.8-V operation and SSC capability in a smaller 14-pin footprint but lacks the second PLL and two extra outputs-making it optimal for cost- and space-sensitive 3-clock applications where dual-PLL flexibility is unnecessary.
Availability
CDCEL913PWR is available at Aetrix Electronics and suitable for digital television, USB 2.0 host controller, Wi-Fi/BT combo module, and DaVinci™ video processor applications requiring stable component supply, long-term lifecycle management, and traceable sourcing.
Supply support for CDCEL913PWR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader delivering analog, embedded processing, and connectivity solutions for industrial, automotive, and consumer markets.
The CDCE(L)9xx family was designed as a flexible, low-power, in-system programmable clock generator platform targeting video, audio, and interface timing in resource-constrained embedded systems.
FAQ
What is the maximum output frequency supported by the CDCEL913PWR?
The CDCEL913PWR supports a maximum LVCMOS output frequency of 230 MHz across all three outputs (Y1/Y2/Y3). This specification holds under recommended operating conditions: VDDOUT = 1.7–1.9 V, TA = –40°C to +85°C, and CL = 15 pF. The device achieves this using its integrated PLL with programmable M/N dividers and maintains 45–55% duty cycle and <0.7 ns rise/fall time at 1.8-V VDDOUT.
Does the CDCEL913PWR support spread-spectrum clocking (SSC), and how is it configured?
Yes, the CDCEL913PWR supports both center-spread and down-spread SSC modulation with selectable amplitudes from 0% to ±2.0%. SSC is configured via the EEPROM or volatile registers using the SSCx[3:0] bits in the PLL1 configuration register. The feature is enabled independently per PLL and can be toggled in real time using the S0/S1/S2 control inputs without reprogramming the device.
How does the CDCEL913PWR differ from the CDCE913PWR in terms of power supply?
The CDCEL913PWR uses a fixed 1.8-V output supply (VDDOUT) for all three LVCMOS outputs, whereas the CDCE913PWR supports either 2.5-V or 3.3-V VDDOUT. This makes the CDCEL913PWR ideal for modern 1.8-V digital SoCs like TI DaVinci™ and OMAP™ processors, eliminating level-shifting requirements and reducing power consumption by ~30% compared to 3.3-V operation.
Can the S1 and S2 pins on the CDCEL913PWR be used for both I²C programming and control functions?
Yes - S1/SDA and S2/SCL are dual-function pins. By default, they operate as I²C serial interface pins (SDA/SCL). Their function can be permanently reconfigured to general-purpose control inputs (S1/S2) by setting bit [6] of EEPROM byte 02h. Once reconfigured, I²C access is disabled unless VDDOUT is forced to GND, which temporarily restores SDA/SCL functionality.
What is the factory default configuration of the CDCEL913PWR after power-up?
Upon power-up, the CDCEL913PWR loads its factory default configuration from EEPROM: Xin/CLK passes directly to all three outputs (Y1/Y2/Y3) at the input frequency (e.g., 27 MHz), with PLL bypassed. S0 controls output enable/disable (3-state vs active), while S1/S2 remain in I²C mode. No external programming is needed for basic operation, enabling immediate use in production before custom configuration.
CDCEL913PWR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 14-TSSOP (0.173", 4.40mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Verified
- Type:
- PLL Clock Synthesizer
- PLL:
- Yes with Bypass
- Input:
- LVCMOS, Crystal
- Output:
- LVCMOS
- Number of Circuits:
- 1
- Ratio - Input:Output:
- 1:3
- Differential - Input:Output:
- No/No
- Frequency - Max:
- 230MHz
- Divider/Multiplier:
- Yes/Yes
- Voltage - Supply:
- 1.7V ~ 1.9V
- Operating Temperature:
- -40°C ~ 85°C
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 14-TSSOP
CDCEL913PWR FAQ
1.How can I place an order for CDCEL913PWR through Aetrix?
Please submit a Request for Quotation (RFQ) for CDCEL913PWR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for CDCEL913PWR reliable?
The price and inventory of CDCEL913PWR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for CDCEL913PWR is usually 5 days.
3.What payment methods are accepted for CDCEL913PWR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for CDCEL913PWR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for CDCEL913PWR?
CDCEL913PWR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your CDCEL913PWR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for CDCEL913PWR?
For technical support, including CDCEL913PWR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your CDCEL913PWR requirements.
6.How does Aetrix verify that CDCEL913PWR is sourced from the original manufacturer or authorized distributors?
All CDCEL913PWR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that CDCEL913PWR meets industry standards.
7.What is the process for return or replacement of CDCEL913PWR?
All CDCEL913PWR units undergo pre-shipment inspection (PSI). If there is an issue with CDCEL913PWR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The CDCEL913PWR part is unused and in its original packaging.
Return procedure for CDCEL913PWR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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