Texas Instruments CDCM61004RHBT

Overview

CDCM61004RHBT from Texas Instruments is a four-output, integrated-VCO clock generator with LVPECL/LVDS/LVCMOS programmable outputs, 1.75–2.05 GHz on-chip VCO, 400 kHz PLL loop bandwidth, and <0.77 ps RMS jitter (625 MHz LVPECL output). It serves as a low-jitter clock synthesizer for high-speed datacom timing in SONET, Ethernet, and Fibre Channel systems.

For engineers reviewing the CDCM61004RHBT datasheet, CDCM61004RHBT pinout, CDCM61004RHBT application, or CDCM61004RHBT equivalent, key selection criteria include its pin-selectable output format, crystal/LVCMOS reference support (21.875–28.47 MHz), 43.75–683.264 MHz output frequency range, industrial temperature rating (–40°C to 85°C), and 5-mm × 5-mm VQFN package.

Technical Context

The CDCM61004RHBT implements a fully integrated LC-based PLL with charge-pump architecture, fixed 400 kHz loop bandwidth, and internal VCO calibration triggered at power-up or RSTN assertion. Its feedback path uses prescaler/feedback divider combinations (e.g., 25/3, 24/3) controlled by PR[1:0] pins.

All four outputs share a single VCO core and are individually configured via OD[2:0] (divider: /1, /2, /3, /4, /6, /8) and OS[1:0] (LVPECL/LVDS/LVCMOS), with one dedicated LVCMOS bypass output (OSC_OUT) for crystal loading control.

Key Specifications

Pinout & Package

The CDCM61004RHBT is housed in a 32-pin, 5.00 mm × 5.00 mm VQFN (RHB) package with exposed thermal pad soldered to ground for thermal management.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar clock generator applications.

Compared with LMK03318RTAR and Si5338A-D-GM, the CDCM61004RHBT offers simpler pin-strapped configuration, lower system cost for fixed-frequency telecom applications, and no software dependency-ideal for high-volume, static-clocking designs where jitter performance below 1 ps is sufficient.

Availability

CDCM61004RHBT is available at Aetrix Electronics and suitable for SONET line cards, Ethernet switch fabrics, Fibre Channel storage controllers, and broadcast video equipment requiring stable component supply over extended production lifecycles.

Supply support for CDCM61004RHBT includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor company specializing in analog, embedded processing, and connectivity technologies with broad industrial and communications portfolio coverage.

The CDCM61004RHBT belongs to TI's high-performance clock generation product line, designed specifically for low-jitter, crystal-referenced timing in wireline datacom infrastructure where pin-strapped simplicity and proven reliability are prioritized over programmability.

FAQ

What is the maximum output frequency supported by the CDCM61004RHBT?

The CDCM61004RHBT supports an output frequency range of 43.75 MHz to 683.264 MHz. This upper limit is achieved using the /1 output divider setting with the VCO operating near 2.05 GHz. The device delivers specified jitter performance (≤0.77 ps RMS) up to 625 MHz in LVPECL mode, making it suitable for 10G Ethernet and OC-192 applications. Frequencies above 625 MHz are characterized for functionality but not guaranteed for jitter compliance per datasheet Table 4.

Does the CDCM61004RHBT require an external crystal or can it use a CMOS clock input?

Yes, the CDCM61004RHBT accepts both a parallel-resonant crystal (21.875–28.47 MHz) directly connected to XIN and a single-ended LVCMOS clock signal within the same frequency range. The internal crystal interface includes programmable load capacitance (8–10 pF), while the LVCMOS input has 10 pF typical input capacitance and 150 kΩ internal pullup resistors. No external components are needed for either source type.

How does the CDCM61004RHBT handle power supply noise sensitivity across its five voltage domains?

The CDCM61004RHBT isolates noise-sensitive blocks using five dedicated 3.3 V supply rails: VCC_IN (input buffer), VCC_PLL1/2 (PLL core), VCC_VCO (VCO tank), and VCC_OUT (output drivers). Each rail requires local 100-nF ceramic + 10-μF Y5V bulk decoupling. REG_CAP1 and REG_CAP2 pins must connect to 10-μF Y5V capacitors referenced to GND to stabilize internal LDOs. This segmentation prevents switching noise from outputs from modulating VCO phase noise.

Can all four outputs of the CDCM61004RHBT operate simultaneously in different logic families?

Yes, each of the four output pairs (OUTP0/OUTN0 through OUTP3/OUTN3) can be independently configured via OS[1:0] control pins to LVPECL, LVDS, or LVCMOS. Additionally, each differential pair can be repurposed as two single-ended LVCMOS outputs. This allows concurrent generation of, for example, LVPECL for backplane SerDes, LVDS for memory interfaces, and LVCMOS for microcontroller peripherals-all from a single CDCM61004RHBT device.

What is the purpose of the OSC_OUT pin on the CDCM61004RHBT?

The OSC_OUT pin provides a buffered LVCMOS replica of the XIN input signal, operating at the same frequency (21.875–28.47 MHz). Its primary function is crystal load tuning: by connecting OSC_OUT back to the crystal's shunt capacitor network, designers actively compensate for parasitic board capacitance and achieve precise reference frequency accuracy without iterative crystal selection. It operates independently of the PLL path and remains active even when CE is deasserted.