Texas Instruments CDCM9102RHBT

Overview

CDCM9102RHBT from Texas Instruments is a low-noise, two-channel 100-MHz clock generator IC with integrated PLL, VCO, and loop filter. It delivers two differential 100-MHz outputs (LVPECL/LVDS/LVCMOS) plus a single-ended 25-MHz oscillator output, all derived from an external 25-MHz crystal. Designed for PCI Express Gen 3 reference clocking, it achieves 21 ps pk-pk period jitter and operates across –40°C to 85°C.

For engineers reviewing the CDCM9102RHBT datasheet, CDCM9102RHBT pinout, CDCM9102RHBT application, or CDCM9102RHBT equivalent, key selection criteria include its 3.3-V operation, configurable output format via OS0/OS1 pins, output enable (OE) control, thermal pad–equipped 5-mm × 5-mm VQFN package, and HCSL interface capability via AC-coupled LVPECL termination.

Technical Context

The CDCM9102RHBT implements a Colpitts crystal oscillator interface for 25-MHz fundamental-mode crystals, with on-chip 10-pF load capacitance and internal LDO-regulated analog/digital supply partitioning to isolate PLL noise. Its PLL architecture includes phase-frequency detector (PFD), charge pump, and pre-programmed feedback dividers targeting fixed 100-MHz outputs.

Output buffer configuration is determined by strapping OS0 and OS1 pins: LVCMOS (00), LVDS (01), LVPECL with OSCOUT disabled (10), or LVPECL with OSCOUT enabled (11). The device supports HCSL signaling through external AC-coupling networks (150-Ω + 471-Ω/56-Ω) and features active-low RESET and OE pins for power-up calibration and shutdown control.

Key Specifications

Pinout & Package

Package: 32-pin VQFN (RHB), 5.0 mm × 5.0 mm body size with exposed thermal pad (GND-connected) for thermal relief.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar clock generator applications.

Compared with CDCM9102RHBT, CDCE925PW offers frequency flexibility at the cost of added configuration complexity, while LMK04806BISQE/NOPB delivers superior jitter performance and scalability but with higher power and BOM cost - CDCM9102RHBT remains optimal for cost-sensitive, fixed-frequency PCIe reference clocking.

Availability

CDCM9102RHBT is available at Aetrix Electronics and suitable for PCI Express Gen 3 reference clocking, Ethernet PHY timing, industrial control backplanes, and test & measurement synchronization requiring stable component supply and guaranteed long-term availability.

Supply support for CDCM9102RHBT includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and clock solutions with over 50 years of innovation in precision timing devices.

The CDCM9102RHBT belongs to TI's low-jitter clock generator product line, engineered specifically for high-reliability communications infrastructure where PCIe Gen 3 timing compliance, thermal robustness, and minimal external component count are critical.

FAQ

What output formats does the CDCM9102RHBT support, and how are they selected?

The CDCM9102RHBT supports LVPECL, LVDS, and LVCMOS output formats on its two 100-MHz differential ports. Selection is performed via hardware strapping of OS0 and OS1 pins (00 = LVCMOS, 01 = LVDS, 10 = LVPECL with OSCOUT off, 11 = LVPECL with OSCOUT on). This eliminates firmware dependencies and ensures deterministic behavior at power-up - a key advantage for the CDCM9102RHBT in PCIe reference clock applications where configuration reliability is essential.

Can the CDCM9102RHBT drive HCSL loads directly, and if not, what is required?

The CDCM9102RHBT does not natively support HCSL signaling but can interface to HCSL receivers using an external AC-coupling network: 150-Ω pull-down resistors at the CDCM9102RHBT LVPECL outputs, plus a 471-Ω/56-Ω resistor divider at the receiver end to establish the correct common-mode voltage (~0.8 V). This configuration is explicitly validated in TI's datasheet for PCIe Gen 1/2/3 compliance and avoids the need for additional level-shifting ICs.

What is the role of the REGCAP1 and REGCAP2 pins on the CDCM9102RHBT?

REGCAP1 and REGCAP2 on the CDCM9102RHBT connect to internal LDO regulators powering the PLL analog core and crystal oscillator circuitry. Each must be decoupled to GND with a 10-μF Y5V capacitor to ensure loop stability and minimize supply-induced jitter. Omitting these capacitors degrades phase noise performance and may cause startup failure - TI specifies this requirement for all CDCM9102RHBT operating conditions.

How does the CDCM9102RHBT achieve PCIe Gen 3 timing compliance?

The CDCM9102RHBT achieves PCIe Gen 3 timing compliance through its ultra-low jitter architecture: 21 ps pk-pk period jitter and 510 fs RMS random jitter (LVPECL mode) fall well within the PCIe Gen 3 specification limit of ≤1.0 ps RMS. Its integrated PLL with on-chip VCO, isolated LDO supplies, and optimized layout guidelines collectively suppress noise sources that degrade timing accuracy - making the CDCM9102RHBT a validated solution for PCIe reference clock generation.

What is the function of the OSCOUT pin on the CDCM9102RHBT, and when is it active?

The OSCOUT pin on the CDCM9102RHBT provides a buffered 25-MHz single-ended CMOS output derived from the internal crystal oscillator. It is active only when both OS0 and OS1 pins are strapped high (11 configuration); otherwise, it remains disabled. This allows designers to use the same CDCM9102RHBT footprint for applications needing either dual 100-MHz clocks alone or combined 100-MHz + 25-MHz timing - enhancing design reuse without changing the bill of materials.