Infineon Technologies CHL8104-11CRT

Overview

CHL8104-11CRT from Infineon Technologies is a dual-loop, 4+1-phase digital buck controller for CPU voltage regulation in Intel VR12 and AMD SVI systems. It supports independent per-phase switching frequencies (200 kHz–1.2 MHz), IR Adaptive Transient Algorithm (ATA), Dynamic Phase Control (DPC), and I²C-based configuration with pin-programmable address. Used in high-performance desktop CPU VRMs.

For engineers reviewing the CHL8104-11CRT datasheet, CHL8104-11CRT pinout, CHL8104-11CRT application, or CHL8104-11CRT equivalent, key selection criteria include VR12/SVI compliance, dual-loop OCP support, thermal monitoring via VRHOT# and TSEN pins, and MTP-configurable fault thresholds for production-ready power delivery design.

Technical Context

The CHL8104-11CRT implements two independent digital PWM control loops-one for main CPU core (4-phase) and one for integrated graphics or auxiliary rail (1-phase)-with fully programmable loop parameters via I²C. It integrates IR Efficiency Shaping with DPC and Active Diode Emulation to optimize efficiency across light-to-heavy loads.

It features dual OCP detection per loop, thermistor-based temperature sensing (TSEN1/TSEN2), VRHOT# assertion, and register-level diagnostics. The controller operates from a single 3.3V ±10%/−15% supply and supports both Intel Mode (SVI2) and AMD Mode (SVI) through dedicated mode-select pins.

Key Specifications

Pinout & Package

CHL8104-11CRT is housed in a 40-pin, 6 mm × 6 mm QFN package with exposed thermal pad (RoHS-compliant, Pb-free).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar digital multi-phase buck controller applications.

Compared with ISL95816IRZ and MP2960GQZ, the CHL8104-11CRT uniquely delivers native dual-loop VR12/SVI compliance, integrated VRHOT# signaling, and MTP-stored configurations-enabling faster qualification and reduced system-level validation effort for client CPU VRMs.

Availability

CHL8104-11CRT is available at Aetrix Electronics and suitable for high-performance desktop CPU VRMs, AMD SVI-based motherboards, and Intel VR12-compliant server platforms requiring stable component supply and long-term lifecycle support.

Supply support for CHL8104-11CRT includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Infineon Technologies is a German semiconductor leader specializing in power management, automotive MCUs, and industrial control ICs, with broad expertise in digital power conversion.

The CHL8104-11CRT belongs to Infineon's IR Digital Power family, engineered specifically for high-efficiency, low-latency CPU voltage regulation in client and entry-server computing platforms.

FAQ

What is the function of the ADDR/PROT/EN_L2 pin on CHL8104-11CRT?

This pin serves three roles: sets I²C address bits (ADDR), enables SMBus packet error checking (PROT), and activates the auxiliary L2 control loop (EN_L2). Its state at power-up determines initial configuration mode-Intel (high), AMD (low), or disabled (floating)-and must be pulled with appropriate resistor networks per design requirements.

Does CHL8104-11CRT support both VR12 and SVI protocols simultaneously?

No-it supports either Intel VR12 (SVI2) or AMD SVI mode, selected at power-up via the MODE pin (Pin 1). In Intel Mode, it implements full SVID timing and VR_READY handshake; in AMD Mode, it follows SVI clock/data framing and voltage command encoding. Both modes share identical hardware but require different firmware configuration.

How does IR Adaptive Transient Algorithm (ATA) reduce output capacitance?

ATA dynamically adjusts PWM duty cycle and phase activation in sub-microsecond intervals during load transients, minimizing voltage deviation without relying on large bulk capacitors. Bench tests show ≤12 mV droop with only 4× 220 µF X7R ceramics under 100 A/µs CPU load steps-reducing total capacitance by ≥35% versus conventional PID-based controllers.

Can CHL8104-11CRT operate without I²C configuration?

Yes-the device boots from factory-default MTP settings, enabling immediate operation with basic VR12 functionality (fixed VID, default OCP thresholds, 4-phase enabled). Full feature access-including ATA tuning, DPC behavior, and thermal limits-requires I²C programming via IR's Digital Power Design Center (DPDC) GUI or custom host firmware.