Microchip Technology CORESRIO-OM

Overview

CORESRIO-OM from Microchip Technology is a licensable Serial RapidIO v2.0 endpoint IP core targeting FPGA-based chip-to-chip and board-to-board interconnects in high-performance embedded systems. It implements full Physical, Logical, and Transport Layers compliant with RapidIO v2.0 Parts 1, 3, and 6, supports AXI4-Lite for register configuration and dual AXI4-Stream interfaces (initiator/target) for packet I/O and maintenance traffic, and delivers up to 250 MHz lane clock operation on PolarFire SoC devices.

For engineers reviewing the CORESRIO-OM datasheet, CORESRIO-OM pinout, CORESRIO-OM application, or CORESRIO-OM equivalent, this page provides verified functional scope, supported device families (PolarFire® SoC, PolarFire, RT PolarFire, RTG4™, IGLOO® 2, SmartFusion® 2), clock domain partitioning (SYS_CLK/ACLK/LANE0_TX_CLK/LANE0_RX_CLK), buffer depth (32-packet TX/RX), and protocol-level feature coverage including NREAD/NWRITE_R/ATOMIC/MAINTENANCE packet types - all critical for SRIO subsystem integration and timing closure.

Technical Context

CORESRIO-OM operates as a fully synthesizable RTL IP core with three layered architecture: Logical Layer handles AXI4-Lite register access and AXI4-Stream packet assembly/disassembly; Buffer Layer implements round-robin scheduling and receiver-controlled flow control with 32-packet transmit/receive buffers; Physical Layer performs 8B/10B encoding/decoding, CRC-5/CRC-16 generation/checking, IDLE1 sequence insertion, and elastic buffering for ±200 ppm clock tolerance.

The core requires four distinct clock domains: SYS_CLK (100 MHz) for system logic, ACLK (100 MHz) for AXI4-Lite interface, and separate LANE0_TX_CLK/LANE0_RX_CLK (up to 250 MHz) for transceiver PMA/PCS interfacing. It supports 34-bit addressing, 8/16/32-bit Device ID, optional endian conversion, and single virtual channel operation - with no support for doorbell messaging, multiple virtual channels, or transmitter-controlled flow control per v2.0 release.

Key Specifications

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar SRIO endpoint applications.

Compared with Xilinx LogiCORE IP Serial RapidIO v10.2 and Intel Serial RapidIO IP Core v19.1, CORESRIO-OM offers tighter integration with Libero SoC v12.0+, lower LUT/DFF utilization (6105/4965 on MPFS250T), and streamlined AXI4-Stream interface mapping - making it the optimal choice for single-lane, cost-sensitive, and Microchip-FPGA-native SRIO endpoint deployments.

Availability

CORESRIO-OM is available at Aetrix Electronics and suitable for radar signal processing subsystems, avionics data concentrators, defense electronic warfare platforms, industrial machine vision hubs, and FPGA-based high-speed interconnect designs requiring stable component supply and long-term IP license continuity.

Supply support for CORESRIO-OM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Microchip Technology Inc. is a global provider of microcontrollers, analog components, FPGAs, and configurable IP solutions, with emphasis on reliability, security, and long-life product support for industrial, aerospace, and automotive markets.

CORESRIO-OM belongs to Microchip's FPGA IP core portfolio designed specifically for high-integrity, low-latency chip-to-chip communication in radiation-tolerant and safety-critical systems built on PolarFire SoC, RTG4, and SmartFusion 2 platforms.

FAQ

What is the licensing model for CORESRIO-OM?

CORESRIO-OM is offered in three license versions: Evaluation (free, obfuscated/encrypted RTL with 4-hour self-destruct), Obfuscated (purchased, encrypted RTL with unlimited silicon use), and RTL (purchased, clear-text Verilog/VHDL source). All versions implement identical functionality; the Evaluation version is intended for architectural validation prior to license purchase. CORESRIO-OM licensing is managed through Microchip's IP catalog in Libero SoC v12.0 or later.

Which FPGA families support CORESRIO-OM implementation?

CORESRIO-OM is validated for implementation on six Microchip FPGA families: PolarFire® SoC (e.g., MPFS250T), PolarFire (e.g., MPF300T), RT PolarFire, RTG4™ (e.g., RT4G150), IGLOO® 2 (e.g., M2GL150TS), and SmartFusion® 2 (e.g., M2S150TS). Resource utilization varies by family - for example, CORESRIO-OM consumes 6105 LUTs and 4965 DFFs on MPFS250T with 100 MHz SYS_CLK and 250 MHz lane clocks.

Does CORESRIO-OM support multi-lane or multi-port configurations?

No. CORESRIO-OM v2.0 supports only single-lane (1x) operation and single-port configuration. Multi-lane operation, multiple virtual channels, multiple port configuration, and priority/critical request flow are explicitly listed as "Features Not Supported in this Release" in the official user guide. CORESRIO-OM is designed for point-to-point or simple star-topology SRIO links, not mesh or switch-fabric deployments.

How does CORESRIO-OM handle clock domain crossing between logic and transceiver layers?

CORESRIO-OM implements dedicated clock domain crossing (CDC) logic between its SYS_CLK/ACLK domains and LANE0_TX_CLK/LANE0_RX_CLK domains. The Physical Layer includes an elastic buffer that compensates for ±200 ppm frequency offset between recovered transceiver clock and logic clock, while AXI4-Stream interfaces use handshake-based valid/ready signaling to safely cross boundaries. CORESRIO-OM requires four independent clock inputs - no internal PLL or clock generation is provided.

What packet types and atomic operations does CORESRIO-OM support?

CORESRIO-OM supports all core RapidIO v2.0 packet types: NREAD, NWRITE, NWRITE_R, SWRITE, MAINTENANCE, RESPONSE, and ATOMIC. Atomic operations include Set, Clear, Increment, Decrement, Swap, Test-and-Swap, and Compare-and-Swap - all implemented in hardware with full CRC-16 protection. Unsupported operations include doorbell messaging and canceling packets, which are documented as omitted in the v2.0 release.