Microchip Technology CORESRIO-RM

Overview

CORESRIO-RM from Microchip Technology is a configurable Serial RapidIO v2.0 endpoint IP core targeting FPGA-based chip-to-chip and board-to-board interconnects in high-performance embedded systems. It implements full Logical, Buffer, and Physical Layers compliant with RapidIO v2.0 Parts 1, 3, and 6, supports AXI4-Lite register configuration and AXI4-Stream data interfaces, delivers up to 250 MHz lane clock operation, and enables 34-bit addressing with 8/16/32-bit Device ID support for real-time signal processing and defense avionics backplanes.

For engineers reviewing the CORESRIO-RM datasheet, CORESRIO-RM pinout, CORESRIO-RM application, or CORESRIO-RM equivalent, this page provides verified functional scope, supported device families (PolarFire® SoC, PolarFire, RTG4™, IGLOO® 2, SmartFusion® 2), AXI4-Stream packet handling behavior, physical layer constraints (Baud Rate Class 1, 1x lane, 8B/10B encoding), and licensing options (Evaluation, Obfuscated, RTL) critical for FPGA integration planning.

Technical Context

CORESRIO-RM implements a three-layer SRIO stack: Logical Layer handles AXI4-Lite register access and AXI4-Stream packet routing for NREAD/NWRITE/NWRITE_R/SWRITE/ATOMIC/MAINTENANCE/RESPONSE packets; Buffer Layer uses round-robin scheduling and receiver-controlled flow control with 32-packet transmit/receive depth.

Physical Layer operates at Baud Rate Class 1 with 1x lane, IDLE1 idle sequence, Control Symbol 24, CRC-5 (control symbols) and CRC-16 (packets), 8B/10B encoding/decoding, and supports configurable 10-bit or 20-bit PMA/PCS interface - all synchronized across SYS_CLK (100 MHz), ACLK (100 MHz), LANE0_TX_CLK (up to 250 MHz), and LANE0_RX_CLK (up to 250 MHz) domains.

Key Specifications

Pinout & Package

CORESRIO-RM is a soft IP core, not a physical component - it has no package or pinout. Interface signals are defined per implementation in Libero SoC SmartDesign and include AXI4-Lite (ARESETN, ACLK, AWADDR, AWVALID, etc.), AXI4-Stream (ACLK, ARESETN, TDATA, TVALID, TREADY, TLAST, TUSER), and physical layer clocks (LANE0_TX_CLK, LANE0_RX_CLK, SYS_CLK).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar SRIO endpoint IP applications.

Compared with Xilinx LogiCORE IP Serial RapidIO v9.5 and Intel FPGA IP for Serial RapidIO II, CORESRIO-RM uniquely delivers strict AXI4-Stream port separation (I/O vs. Maintenance), native support for Microchip's PolarFire SoC transceivers, and flexible licensing (free Evaluation version with 4-hour silicon runtime), making it optimal for cost-sensitive, safety-isolated, and vendor-locked FPGA programs.

Availability

CORESRIO-RM is available at Aetrix Electronics and suitable for radar backplanes, multi-core DSP interconnects, avionics vehicle management systems, and ATE data aggregation requiring stable component supply, long-term FPGA IP licensing continuity, and rapid integration into Libero SoC v12.0+ design flows.

Supply support for CORESRIO-RM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Microchip Technology Inc. is a U.S.-based semiconductor manufacturer specializing in microcontrollers, analog devices, FPGAs (PolarFire®, SmartFusion® 2), and configurable IP cores for industrial, aerospace, and defense applications.

CORESRIO-RM belongs to Microchip's FPGA IP portfolio and was designed specifically to accelerate SRIO-based chip-to-chip communication in radiation-tolerant, power-efficient, and security-hardened FPGA systems - particularly those built on PolarFire SoC and RTG4™ platforms.

FAQ

What is CORESRIO-RM and how does it differ from a physical SRIO transceiver?

CORESRIO-RM is a synthesizable RTL IP core - not a physical IC - that implements the Serial RapidIO v2.0 Logical, Buffer, and Physical Layers inside Microchip FPGAs. Unlike discrete SRIO transceivers, it integrates directly into the FPGA fabric, uses AXI4-Lite and AXI4-Stream interfaces for host connectivity, and relies on the FPGA's built-in transceivers (e.g., PolarFire SoC's SERDES) for electrical signaling. CORESRIO-RM requires no external components and is configured via Libero SoC.

Which FPGA families officially support CORESRIO-RM?

CORESRIO-RM is validated and documented for use on six Microchip FPGA families: PolarFire® SoC (e.g., MPFS250T), PolarFire (e.g., MPF300T), RT PolarFire, RTG4™ (e.g., RT4G150), IGLOO® 2 (e.g., M2GL150TS), and SmartFusion® 2 (e.g., M2S150TS). Performance metrics (LUT/DFF/RAM usage, max clock frequencies) are provided per family in DS50003490A, and all require Libero SoC v12.0 or later.

Does CORESRIO-RM support multi-lane or multi-port configurations?

No. CORESRIO-RM supports only single-lane (1x) operation and a single port. The documentation explicitly lists "Multiple Port configuration" and "Multiple Virtual Channel" as features *not supported* in this release. All timing, buffer, and physical layer resources are dimensioned for one lane - LANE0_TX_CLK and LANE0_RX_CLK are the only supported clock inputs, and no alternate lane interfaces are defined in the RTL or configurator.

What licensing options are available for CORESRIO-RM?

CORESRIO-RM is offered in three license versions: (1) Evaluation - free, obfuscated/encrypted RTL with 4-hour self-destruct timer on silicon; (2) Obfuscated - purchased license with encrypted RTL, unlimited runtime, and license-locking; (3) RTL - purchased license with clear, unencrypted Verilog/VHDL source code and unlimited runtime. All versions implement identical functionality; only delivery format and usage restrictions differ.

Can CORESRIO-RM be used with non-Microchip FPGAs?

No. CORESRIO-RM is tightly coupled to Microchip's FPGA architecture and toolchain. Its Physical Layer relies on Microchip-specific transceiver primitives (e.g., PolarFire SERDES PMA/PCS blocks), its timing constraints assume Microchip clock networks, and installation requires Libero SoC IP Catalog integration. The User Guide states explicit support only for Microchip device families and mandates Libero SoC v12.0+, confirming it is not portable to Xilinx, Intel, or Lattice platforms.