STMicroelectronics CS70P

Overview

CS70P from STMicroelectronics is a high-side current sense amplifier with independent supply and input common-mode voltage domains, 20–100 V/V pin-selectable gain, ±500 µV max input offset voltage, and operation from -40 °C to +125 °C in TSSOP8 package. It measures differential voltage across a high-side shunt (e.g., in wireless battery chargers) and delivers ground-referenced buffered output for microcontroller ADC interfacing.

For engineers reviewing the CS70P datasheet, CS70P pinout, CS70P application, or CS70P equivalent, this device supports precision high-voltage current monitoring in single- or dual-supply configurations, with critical attention to common-mode rejection (90–105 dB), supply current (<360 µA), gain accuracy (±2.5% typ.), output voltage drift (±240 ppm/°C), and reversed-battery survivability (-16 V to 75 V).

Technical Context

The CS70P employs a current-feedback architecture with internal resistor ratio (K1 = Rg3/Rg1 = 20 V/V) and programmable buffer gain (K2 = 1, 1.25, 2.5, or 5) to achieve total gains of 20, 25, 50, or 100 V/V. Its input stage operates independently of supply rails, enabling true high-side sensing where Vp and Vm float up to 70 V above GND in single-supply mode.

It features dual-supply capability via Vcc− pin, shifting common-mode range to −2.1 V to 65 V when Vcc− = −5 V, and includes robust protection: ±20 V differential input limit, −16 V to 75 V common-mode survival, and 2.5 kV HBM ESD rating. Output stage provides rail-to-rail sourcing/sinking (±10 mA) with <135 mV saturation voltage.

Key Specifications

Pinout & Package

TSSOP8 plastic package (8-pin, 3 mm × 4.4 mm, 0.65 mm pitch), ECOPACK® compliant, thermal resistance R_thJA = 120 °C/W.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar high-side current sense amplifier applications.

Compared with MAX4080TASA+ and INA240A1QDRQ1, the CS70P uniquely combines quad-gain selection, ultra-low ICC (<360 µA), and TSSOP8 size - making it optimal for space- and power-constrained consumer electronics where flexible current-range scaling is essential.

Availability

CS70P is available at Aetrix Electronics and suitable for wireless battery chargers, portable equipment chargers, and precision current sources requiring stable component supply across industrial and consumer production cycles.

Supply support for CS70P includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing analog, microcontroller, power, and sensor solutions for industrial, automotive, and consumer markets.

The CS70P belongs to ST's high-voltage precision analog portfolio, engineered specifically for robust, low-power current sensing in battery-powered and high-common-mode industrial systems - emphasizing reliability under harsh electrical conditions.

FAQ

What is the maximum common-mode voltage the CS70P can survive during load-dump events?

The CS70P survives common-mode voltages from −16 V to +75 V, verified per absolute maximum ratings. This covers ISO 7637-2 Pulse 5a (load-dump) up to 75 V and reverse-battery conditions down to −16 V without damage or latch-up, provided Vcc+–Vcc− remains ≤15 V and external clamping is used per application guidelines.

Can the CS70P operate with Vcc− floating or disconnected?

No - Vcc− must be either tied to GND (single-supply mode) or connected to a defined negative voltage (dual-supply mode). Floating Vcc− violates the absolute maximum rating for Vcc+–Vcc− and risks undefined behavior or damage. In single-supply operation, Vcc− and GND are shorted externally per datasheet Figure 1.

How does gain selection affect output accuracy at low Vsense values?

At Vsense = 5 mV, output accuracy degrades to ±10% (max) for all gains due to fixed input offset voltage contribution. Higher gains (e.g., 100 V/V) amplify both signal and offset equally - so absolute error in mV increases, but percentage error at low Vsense is dominated by Vos. For best low-current resolution, use highest feasible gain and calibrate out Vos in firmware.

Is the CS70P compatible with 1.8 V GPIO for SEL1/SEL2 control?

No - SEL1 and SEL2 logic thresholds require VIH ≥ 1.2 V (min) with VCC ≥ 2.7 V, but the pins are referenced to GND and tolerate only −0.3 V to Vcc++0.3 V. A 1.8 V GPIO may not reliably assert VIH when Vcc+ = 2.7 V (VIH min = 1.2 V, but margin is tight); use level-shifting or ensure Vcc+ ≥ 3.3 V for robust 1.8 V control.