Infineon Technologies CY15B104QI-20LPXI
- Part No.:
- CY15B104QI-20LPXI
- Manufacturer:
- Infineon Technologies
- Category:
- Memory
- Package:
- 8-UQFN
- Datasheet:
-
CY15B104QI-20LPXI.pdf
- Description:
- IC FRAM 4MBIT SPI 20MHZ 8GQFN
- Quantity:
- Payment:

- Shipping:

Inventory:1,763
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Product details
Overview
CY15B104QI-20LPXI from Infineon is a 4-Mbit serial ferroelectric RAM (F-RAM) organized as 512K × 8, operating over SPI at up to 20 MHz with 1.8 V–3.6 V supply, 10¹⁵ read/write endurance, and 151-year data retention-deployed in industrial data logging systems requiring instant nonvolatile writes without write delays.
For engineers reviewing the CY15B104QI-20LPXI datasheet, CY15B104QI-20LPXI pinout, CY15B104QI-20LPXI application, or CY15B104QI-20LPXI equivalent, key selection criteria include SPI mode 0/3 compatibility, hardware/software write protection (WP pin + WRDI instruction), dedicated 256-byte reflow-survivable special sector, and ultra-low deep power-down current (0.70 µA).
Technical Context
The CY15B104QI-20LPXI implements an SPI slave interface with zero-latency write architecture: data commits immediately upon byte transfer completion, eliminating polling and enabling deterministic timing for high-frequency data capture. Its ferroelectric memory array requires no erase cycles and supports full-speed reads/writes across all 512K addresses using standard 3-byte addressing.
It integrates dual-layer write protection-hardware via active-low WP pin (enforced when WPEN=1 in status register) and software via WRDI instruction plus configurable block protection (1/4, 1/2, or full array). The device also embeds manufacturer ID, product ID, unique device ID, and user-writable 8-byte serial number registers.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory density | 4 Mbit (512K × 8), enabling compact storage of firmware metadata or sensor history without external buffering |
| SPI clock max | 20 MHz, supporting 2.5 MB/s sustained write throughput with no wait states |
| Endurance | 10¹⁵ read/write cycles, permitting continuous logging at 1 kHz for >31,700 years without wear-out |
| Data retention | 151 years at +85°C, ensuring archival integrity in unpowered industrial edge nodes |
| Supply voltage | 1.8 V to 3.6 V, compatible with both 1.8 V logic domains and legacy 3.3 V systems |
| Deep power-down current | 0.70 µA (typ), reducing standby energy in battery-backed metering or IoT endpoints |
| Special sector | 256-byte dedicated F-RAM sector surviving ≥3 reflow cycles, ideal for storing calibration or board identity |
Pinout & Package
Package: 8-pin ultra-thin fine-pitch land grid array (UFLGA), 2.0 mm × 2.5 mm × 0.5 mm, RoHS-compliant, industrial-grade thermal performance.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| CS | Chip select input | Active-low enable: drives device into standby (tristate I/O, 2.3 µA) when HIGH; initiates SPI transaction on falling edge |
| SCK | Serial clock input | Synchronizes all I/O; inputs latched on rising edge, SO driven on falling edge; supports 0–20 MHz with interruptible clock |
| SI | Serial data input | Receives opcodes, addresses, and write data; must be held valid to meet IDD specs; supports shared SI/SO configuration |
| SO | Serial data output | Drives read data and status bits only during active read; tristated otherwise; transitions on SCK falling edge |
| WP | Write protect input | Hardware lock for status register writes when WPEN=1; must tie to VDD if unused to prevent spurious protection |
| VSS | Ground | System reference return path; mandatory connection for stable core and I/O operation |
| VDD | Power supply | 1.8–3.6 V input; powers internal logic, F-RAM array, and I/O buffers; includes inrush current control circuitry |
| DNU | Do-not-use terminal | No internal connection; must float or tie to VDD-no routing or PCB pad required |
Key Features
| Feature | Design Value |
|---|---|
| Instant nonvolatile write | Zero latency: data written to array immediately after byte transfer; no polling or timeout handling needed in host firmware |
| Virtually unlimited endurance | 10¹⁵ cycles enables real-time event logging in PLCs or medical devices without wear leveling or block management |
| Dual write protection | Hardware (WP pin) + software (WRDI + block lock bits) prevents accidental corruption of critical configuration or calibration data |
| Reflow-survivable sector | 256-byte special sector retains content through ≥3 standard Pb-free reflow profiles-ideal for post-manufacturing programming |
| Low-power modes | Four-tier power management: standby (2.3 µA), deep power-down (0.70 µA), hibernate (0.1 µA), and controlled inrush (1.5 mA) |
Applications
| Industrial Data Logger | Smart Energy Meter |
|---|---|
Use Scenario: Continuous timestamped recording of voltage/current samples at 10 kHz in harsh environments with frequent power loss. IC Role / Device Role / Timing Role: Nonvolatile scratchpad memory holding last 5 seconds of raw ADC data before flash backup. Use Value: Eliminates risk of data loss during brownouts due to zero-write-delay architecture and 10¹⁵ endurance. | Use Scenario: Storing tamper logs, tariff tables, and cryptographic keys in utility-grade meters certified to IEC 62056. IC Role / Device Role / Timing Role: Secure, long-retention configuration store interfaced via isolated SPI from metrology MCU. Use Value: 151-year retention and reflow-survivable sector ensure field-deployed unit identity remains intact over 20+ year service life. |
| Medical Diagnostic Sensor Hub | Automotive ADAS Calibration Module |
Use Scenario: Capturing burst-mode ECG waveforms during patient stress tests where power interruptions may occur mid-acquisition. IC Role / Device Role / Timing Role: High-speed buffer between analog front-end and low-power application processor. Use Value: 20 MHz SPI bandwidth and instant write enable real-time waveform streaming without FIFO overflow or data gaps. | Use Scenario: Storing camera lens distortion coefficients and radar alignment offsets updated during vehicle service. IC Role / Device Role / Timing Role: Field-programmable nonvolatile memory accessible via CAN-to-SPI bridge during dealership diagnostics. Use Value: Hardware WP pin prevents inadvertent overwrite during service; special sector stores immutable calibration signatures. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial nonvolatile memory applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| CY15B104QN-20LPXI | Same die, UFLGA package but with NRND status per Infineon documentation; identical electrical specs and pinout | Not recommended for new designs; suitable only for legacy design continuity or obsolescence mitigation | Select only if maintaining existing BOM with CY15B104QN-20LPXI footprint and lifecycle commitment |
| FM25V04-G | Cypress (now Infineon) 4-Mbit F-RAM; 2.7–3.6 V supply only; no special sector; 10 MHz max SPI speed | Lacks reflow-survivable sector and 20 MHz performance; limited to 3.3 V systems without level-shifting | Choose when 3.3 V operation suffices and reflow resilience is not required; lower cost in volume |
Compared with CY15B104QN-20LPXI, the -20LPXI variant maintains full support status and identical functionality; versus FM25V04-G, it delivers 2× SPI bandwidth, wider voltage range, and production-ready special-sector capability for board-level traceability.
Availability
CY15B104QI-20LPXI is available at Aetrix Electronics and suitable for industrial data loggers, smart energy meters, medical diagnostic sensor hubs, and automotive ADAS calibration modules requiring stable component supply across extended temperature ranges and long product lifecycles.
Supply support for CY15B104QI-20LPXI includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Infineon Technologies is a German semiconductor leader specializing in power management, sensing, and security solutions for industrial, automotive, and IoT markets.
The EXCELON™ LP F-RAM product line targets high-reliability, high-endurance nonvolatile memory applications where flash/EEPROM limitations-write latency, endurance fatigue, and power spikes-compromise system robustness.
FAQ
Is CY15B104QI-20LPXI pin-compatible with standard SPI EEPROMs or flash devices?
Yes-it uses an industry-standard 8-pin SPI pinout (CS, SCK, SI, SO, WP, VSS, VDD, DNU) matching common serial NOR flash and EEPROM packages. No PCB redesign is needed for drop-in replacement, though firmware must disable polling loops due to instant-write behavior.
Does the 256-byte special sector require separate addressing or command set?
No-the special sector resides at fixed address 0x7F000–0x7F0FF and is accessed using standard READ/WRITE opcodes (0x03/0x02); no dedicated commands are needed. Its reflow resilience stems from process-level metallization, not logical isolation.
What is the functional impact of the DNU pin being left floating?
Leaving the DNU pin floating has no electrical or functional impact-it is internally unconnected. Infineon explicitly permits this configuration; tying it to VDD is optional and provides no benefit unless board layout constraints require termination.
How does inrush current control operate during power-up?
The device limits peak inrush to 1.5 mA (typ) by staging internal power-rail activation-delaying F-RAM array biasing until VDD stabilizes-preventing system rail droop that could reset adjacent logic in dense PCB layouts.
CY15B104QI-20LPXI Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Infineon Technologies
- Series:
- Excelon™-LP,F-RAM™
- Package/Case:
- 8-UQFN
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- FRAM
- Technology:
- FRAM (Ferroelectric RAM)
- Memory Size:
- 4Mbit
- Memory Organization:
- 512K x 8
- Memory Interface:
- SPI
- Clock Frequency:
- 20 MHz
- Write Cycle Time - Word, Page:
- -
- Access Time:
- -
- Voltage - Supply:
- 1.8V ~ 3.6V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-GQFN (3.23x3.28)
CY15B104QI-20LPXI FAQ
1.How can I place an order for CY15B104QI-20LPXI through Aetrix?
Please submit a Request for Quotation (RFQ) for CY15B104QI-20LPXI on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for CY15B104QI-20LPXI reliable?
The price and inventory of CY15B104QI-20LPXI are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for CY15B104QI-20LPXI is usually 5 days.
3.What payment methods are accepted for CY15B104QI-20LPXI?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for CY15B104QI-20LPXI transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for CY15B104QI-20LPXI?
CY15B104QI-20LPXI orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your CY15B104QI-20LPXI order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for CY15B104QI-20LPXI?
For technical support, including CY15B104QI-20LPXI datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your CY15B104QI-20LPXI requirements.
6.How does Aetrix verify that CY15B104QI-20LPXI is sourced from the original manufacturer or authorized distributors?
All CY15B104QI-20LPXI products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that CY15B104QI-20LPXI meets industry standards.
7.What is the process for return or replacement of CY15B104QI-20LPXI?
All CY15B104QI-20LPXI units undergo pre-shipment inspection (PSI). If there is an issue with CY15B104QI-20LPXI, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The CY15B104QI-20LPXI part is unused and in its original packaging.
Return procedure for CY15B104QI-20LPXI:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
CY15B104QI-20LPXI Tags

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M24C02-WMN6TP
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AT24C02C-XHM-T
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AT21CS01-STUM10-T
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