Infineon Technologies CY28158OXC

Overview

CY28158OXC from Cypress Semiconductor is a spread-spectrum clock generator IC designed for ServerWorks chipset platforms, delivering six skew-controlled CPU clocks (100/133 MHz), six PCI clocks (33.33 MHz), two 66.67 MHz 3V66 outputs, three 16.67 MHz IOAPIC clocks, one 48.008 MHz USB clock, and two 14.318 MHz reference clocks - all with <150 ps CPU output jitter and 0.5% downspread EMI reduction.

For engineers reviewing the CY28158OXC datasheet, CY28158OXC pinout, CY28158OXC application, or CY28158OXC equivalent, key selection criteria include spread-spectrum enable control (SPREAD#), CPU/PCI clock stop capability (CPU_STOP#/PCI_STOP#), programmable 100/133 MHz operation via SEL pins, multi-rail supply support (2.5V/3.3V), and strict skew budgets across CPU, PCI, and IOAPIC domains.

Technical Context

The CY28158OXC integrates dual PLLs: PLL1 generates the CPU clock and drives all synchronous outputs (PCI, 3V66, IOAPIC, USB) with deterministic phase offsets; PLL2 provides free-running PCI_F and supports crystal-based reference generation. Spread spectrum modulation is applied only to PLL1's VCO, enabling up to 10 dB EMI reduction without affecting PLL2-stabilized reference or free-running outputs.

It implements hierarchical clock gating: CPU_STOP# disables CPU and 3V66 outputs within ≤3 CPU cycles; PCI_STOP# gates PCI[1–5] and PCI_F independently; PWR_DWN# places the entire device into <200 µA shutdown mode. All outputs feature configurable drive strength (Type 1/3/5 buffers) and are electrically isolated by dedicated power/ground rails per voltage domain.

Key Specifications

Pinout & Package

Package: 56-pin Small Outline Plastic Package (SSOP), 0.635 mm pitch, JEDEC MS-013AC compliant, body size 18.4 mm × 7.5 mm.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar clock generator applications.

Compared with ICS952006AGT and ICS952010AGT, the CY28158OXC uniquely delivers full ServerWorks GC-LE clocking coverage - including 2.5V CPU/IOAPIC domains, six skew-controlled CPU clocks, and native 16.67 MHz IOAPIC timing - making it irreplaceable in legacy server motherboard revisions.

Availability

CY28158OXC is available at Aetrix Electronics and suitable for server motherboard manufacturing, industrial embedded computing, and legacy chipset upgrade programs requiring stable component supply and long-term lifecycle support.

Supply support for CY28158OXC includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Cypress Semiconductor (now part of Infineon) is a fabless semiconductor company specializing in timing, memory, microcontrollers, and USB connectivity solutions for computing and industrial markets.

The CY28xxx spread-spectrum clock generator product line was engineered specifically for x86 server and workstation platforms using ServerWorks, Intel, and VIA chipsets - prioritizing EMI compliance, multi-domain skew control, and seamless integration with northbridge clock trees.

FAQ

What is the function of the SPREAD# pin, and how does it affect EMI performance?

The SPREAD# pin is an active-low control that enables or disables Cypress's proprietary 0.5% downspread modulation on the CPU, PCI, IOAPIC, and USB output clocks. When asserted (low), it reduces peak radiated emissions by up to 10 dB without altering frequency accuracy or introducing jitter beyond the specified <150 ps cycle-cycle limit. It has no effect on REF or PCI_F outputs.

Can CY28158OXC operate with only a 3.3V supply, or are both 2.5V and 3.3V rails mandatory?

Both 2.5V (VDD_CPU, VDD_IOAPIC) and 3.3V (VDD_REF, VDD_PCI, VDD_3V66, VDD_48MHZ, VDDA) supplies are mandatory. The CPU and IOAPIC output drivers require 2.5V for correct logic thresholds and drive strength; applying 3.3V to those pins exceeds absolute maximum ratings and risks permanent damage. Decoupling capacitors must be placed per supply domain as specified in the layout guidelines.

How does CPU_STOP# differ from PWR_DWN# in terms of functionality and power savings?

CPU_STOP# disables only the CPU and 3V66 clock outputs while keeping PLLs, REF, PCI_F, and internal logic active - resulting in ~90 mA IDD2 current draw. PWR_DWN# shuts down the entire device except bias circuitry, reducing current to <200 µA. CPU_STOP# responds within ≤3 CPU cycles; PWR_DWN# requires full re-lock time (~3 ms) upon exit, making it suitable for deep sleep states only.

Is the 48 MHz USB clock output guaranteed to meet USB 2.0 specification jitter requirements?

No - the CY28158OXC's 48 MHz output has 500 ps cycle-cycle jitter, exceeding the USB 2.0 full-speed requirement of <150 ps RMS (≈212 ps peak-to-peak). It is intended for non-critical USB peripheral clocking or as a secondary reference; a dedicated USB-compliant oscillator or PLL is required for host controller compliance.