Infineon Technologies CY28158OXCT

Overview

CY28158OXCT from Cypress Semiconductor is a spread-spectrum clock generator IC designed for ServerWorks chipset platforms, delivering six skew-controlled 100/133 MHz CPU clocks, six synchronous 33.3 MHz PCI clocks, two 66.67 MHz 3.3V AGP clocks, three 16.67 MHz IOAPIC clocks, one 48.008 MHz USB clock, and two 14.318 MHz reference clocks - all with <150 ps CPU output jitter and 0.5% downspread EMI reduction.

For engineers reviewing the CY28158OXCT datasheet, CY28158OXCT pinout, CY28158OXCT application, or CY28158OXCT equivalent, key selection criteria include CPU/PCI/IOAPIC clock synchronization timing offsets (0–4.0 ns), dual-supply operation (2.5V CPU/IOAPIC + 3.3V peripheral rails), SSOP-56 package thermal limits (T_J ≤ 150°C), and programmable 100/133 MHz CPU frequency via SEL133/100# pin.

Technical Context

The CY28158OXCT integrates two PLLs: PLL1 generates the CPU clock (100 or 133 MHz) with spread-spectrum modulation applied to reduce EMI; PLL2 derives PCI, 3V66, IOAPIC, REF, and 48 MHz outputs synchronously from the CPU clock. All outputs are buffered using voltage-specific driver types (Type 1 for 2.5V, Type 3/5 for 3.3V) with impedance control (12–60 Ω).

Timing coordination is managed via dedicated control pins: CPU_STOP# halts CPU and 3V66 clocks in ≤3 cycles; PCI_STOP# disables PCI outputs independently; PWR_DWN# places the device into low-power shutdown (IDDPD2 = 100 µA); SPREAD# enables/disables downspread modulation. Frequency selection uses three-pin encoding (SEL133/100#, SEL1, SEL0) per documented function table.

Key Specifications

Pinout & Package

The CY28158OXCT is housed in a 56-pin Small Outline Plastic Package (SSOP), 0.300-inch body width, with 0.025-inch lead pitch. Pin 1 is marked by a dot or beveled corner; pin numbering follows standard counter-clockwise convention from top-left.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar clock generator applications.

Compared with IDT 87012BGI and ICS 952002AF, the CY28158OXCT uniquely integrates ServerWorks-specific timing offsets (CPU-to-3V66, CPU-to-IOAPIC), native 48 MHz USB output, and dual-supply buffering - making it irreplaceable in validated GC-LE/GC-HE reference designs without hardware revision.

Availability

CY28158OXCT is available at Aetrix Electronics and suitable for server motherboard manufacturing, enterprise storage controller development, and industrial compute module production requiring stable component supply and long-term lifecycle support.

Supply support for CY28158OXCT includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Cypress Semiconductor (now part of Infineon) is a U.S.-based semiconductor company specializing in timing, memory, and programmable logic solutions for computing and communications infrastructure.

The CY28158 belongs to Cypress's Spread Spectrum Clock Generator product line, engineered specifically to meet EMI compliance and multi-domain clock synchronization requirements of x86 server platforms using ServerWorks chipsets.

FAQ

What is the maximum allowable capacitive load on the CPU outputs?

The CY28158OXCT CPU outputs are specified for a maximum capacitive load of 30 pF per pin, as defined in the Electrical Characteristics table. Exceeding this limit increases rise/fall time and may degrade duty cycle (45–55%) or cause timing violations on high-speed FSB interfaces. Decoupling capacitors must be placed within 5 mm of each VDD_CPU pin per the test circuit layout.

Can the 48 MHz output be disabled while keeping other clocks active?

No - the 48 MHz output is enabled or disabled solely by the SEL1/SEL0/SEL133/100# pin combination (see Function Table). When SEL1=0, SEL0=1, SEL133/100#=0, 48 MHz is OFF; all other valid configurations enable it. There is no dedicated enable/disable pin or register control for 48MHZ independent of CPU frequency selection.

Does the CY28158OXCT support spread spectrum on individual output banks?

No - spread spectrum modulation is applied globally to the PLL1 output only, affecting all clocks derived from the CPU clock (CPU, PCI, 3V66, IOAPIC, and 48 MHz). REF[0–1] outputs are sourced directly from the crystal oscillator and remain unmodulated, preserving stability for legacy timing functions.

What is the recommended crystal specification for X1/X2?

A parallel-resonant fundamental-mode crystal with nominal frequency 14.318 MHz, load capacitance C_LOAD = 18 pF, and stability ≤ ±50 ppm over 0°C to +70°C is required. The crystal must be placed within 5 mm of X1/X2 pins, with symmetric trace routing and no vias - deviations require adjustment per Cypress Application Note "Crystal Oscillator Topics" (AN2110).