Skyworks Solutions Inc. CY28317PVXC-2

Overview

CY28317PVXC-2 from Silicon Labs is a single-chip system frequency synthesizer designed specifically for VIA PL133T and PLE133T mobile chipsets. It delivers programmable CPU clock outputs from 50 MHz to 248 MHz in <1 MHz increments, supports SMBus-configurable PCI/SDRAM clocks with programmable drive strength and output skew, and integrates a fail-safe watchdog timer with automatic recovery frequency switching. It is used in legacy x86 mobile platform timing subsystems requiring robust clock management and system-level fault recovery.

For engineers reviewing the CY28317PVXC-2 datasheet, CY28317PVXC-2 pinout, CY28317PVXC-2 application, or CY28317PVXC-2 equivalent, key selection considerations include its 48-pin TSSOP package, SMBus-programmable CPU/PCI/SDRAM clock outputs, integrated watchdog timer with recovery frequency mode, spread-spectrum EMI suppression, and hardware/firmware-controlled clock stop and reset generation.

Technical Context

The CY28317PVXC-2 implements dual PLL architecture: one dedicated to CPU clock synthesis (50–248 MHz) with programmable N/M dividers and gear constant selection, and another for PCI/SDRAM/48 MHz outputs derived from fixed-ratio division. Its SMBus interface supports byte/block read/write operations for full register configuration including watchdog timeout scaling (150 ms or 2.5 s prescaler), recovery frequency source selection (latched FS[4:0] or custom N/M values), and output enable/control bits.

It features hardware strapping via FS0–FS4 pins for power-on frequency selection, open-drain RST# assertion on watchdog timeout or frequency change, and differential CPU clock outputs (CPUT/CPUC) with selectable 0.7 V or 1.0 V swing via MULT_SEL and IREF. All outputs support programmable skew-CPU-to-CPU skew ≤175 ps, PCI-to-PCI skew ≤500 ps-and drive strength control per domain (CPU, PCI, SDRAM).

Key Specifications

Pinout & Package

Package: 48-pin TSSOP (lead-free, RoHS-compliant), 7.0 mm × 12.0 mm body, 0.5 mm pitch.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar clock synthesizer applications.

Compared with CY28316PVXC and ICS9LPRS355AKLFT, the CY28317PVXC-2 uniquely combines VIA-specific frequency ratios, integrated watchdog with hardware-enforced recovery mode, and dual-mode (single-ended + differential) CPU clock outputs - making it irreplaceable in validated PL133T/PLE133T mobile designs requiring fault resilience.

Availability

CY28317PVXC-2 is available at Aetrix Electronics and suitable for mobile computing platforms, VIA chipset-based industrial controllers, and legacy embedded systems requiring stable component supply and long-term lifecycle support.

Supply support for CY28317PVXC-2 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Silicon Labs is a fabless semiconductor company specializing in timing, wireless, and sensor solutions, with deep expertise in clock generation and jitter performance.

The CY28317PVXC-2 belongs to Silicon Labs' legacy clock synthesizer product line, engineered specifically for VIA Technologies' PL133T and PLE133T mobile chipsets to deliver integrated, configurable, and fault-resilient system timing.

FAQ

What is the primary function of the CY28317PVXC-2 in a VIA PL133T-based system?

The CY28317PVXC-2 serves as the central system clock synthesizer, generating synchronized CPU, PCI, and SDRAM clocks from a 14.318 MHz crystal. It enables BIOS-configurable CPU frequencies (50–248 MHz), provides hardware-strapped or SMBus-programmed output control, and ensures timing compliance across all VIA PL133T-dependent subsystems. Its design directly maps to the PL133T's clocking architecture, making CY28317PVXC-2 essential for functional timing in these platforms.

Does the CY28317PVXC-2 support differential CPU clock outputs, and how are they configured?

Yes, the CY28317PVXC-2 provides differential CPU clock outputs CPUT and CPUC (Pins 44 and 43). Their output swing is controlled by MULT_SEL (Pin 22) and IREF (Pin 40): MULT_SEL = LOW yields 1.0 V swing; MULT_SEL = HIGH yields 0.7 V swing. The IREF pin sets the reference current (5.00 mA or 2.32 mA) per Table 1, directly determining drive strength and termination matching for differential signaling integrity.

How does the watchdog timer in the CY28317PVXC-2 operate during a system hang?

When enabled (WD_EN = 1), the CY28317PVXC-2 watchdog timer starts counting down after any CPU frequency change. On timeout, it asserts RST# (Pin 41), reloads a preconfigured recovery frequency (from latched FS[4:0] or custom N/M registers), and locks itself into recovery mode - disabling further SMBus frequency updates until WD_EN is cleared by system software. This ensures deterministic fallback without external supervision.

Can the CY28317PVXC-2 generate non-standard PCI clock frequencies, and what limits apply?

No - the CY28317PVXC-2 generates only standard 33 MHz PCI clocks on PCI0_F/FS4, PCI1/FS3, and PCI2:6 outputs. Its internal PLL and divider architecture is fixed for PCI compliance; frequency selection affects only CPU, SDRAM, and 48/24 MHz outputs. PCI outputs derive from a fixed ratio of the main PLL, and their enable/disable state is controlled per-pin via SMBus register bits, but their 33 MHz frequency is immutable.

What package and lead finish does the CY28317PVXC-2 use, and is it RoHS-compliant?

The CY28317PVXC-2 is supplied in a 48-pin TSSOP package (7.0 mm × 12.0 mm, 0.5 mm pitch) with lead-free (Pb-free) matte tin finish, fully compliant with RoHS Directive 2011/65/EU and JEDEC J-STD-020 moisture sensitivity level 3 (MSL3). The "-2" suffix denotes the commercial temperature grade (0 °C to +70 °C), and "PVXC" confirms the TSSOP packaging and Pb-free construction.