My Inquiry
My Account
Infineon Technologies CY28329ZXC
- Part No.:
- CY28329ZXC
- Manufacturer:
- Infineon Technologies
- Package:
- 56-TFSOP (0.240", 6.10mm Width)
- Datasheet:
-
CY28329ZXC.pdf
- Description:
- IC CLOCK DRIVER 56TSSOP
- Quantity:
- Payment:
- Shipping:
Inventory:4,483
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
CY28329ZXC from Cypress Semiconductor is a 133-MHz spread-spectrum clock synthesizer/driver with four differential CPU clock pairs, ten synchronous PCI outputs, six 3.3V 66-MHz clocks, two 48-MHz USB/DOT clocks, and one 14.318-MHz reference output - all in a single 56-pin TSSOP package. It serves as a motherboard clock generator supporting multi-CPU systems, AGP/Hub Link, PCI slots, USB host controllers, and ISA I/O chips.
For engineers reviewing the CY28329ZXC datasheet, CY28329ZXC pinout, CY28329ZXC application, or CY28329ZXC equivalent, this device delivers synchronized, low-jitter clock distribution with SMBus-configurable enable/disable per output, spread-spectrum EMI reduction, and ACPI-compliant power-down control via PD# and PCI_STOP#.
Technical Context
The CY28329ZXC integrates two PLLs: PLL1 generates CPU clocks (100/133 MHz) from a 14.318-MHz crystal input, while PLL2 derives 66-MHz and sub-harmonic clocks (33/48 MHz) for PCI, 3V66, and USB domains. Output buffers are segmented by voltage domain (VDD_CPU, VDD_PCI, VDD_3V66, VDD_48MHz) and impedance type (Type X1 for CPU, Type 5 for PCI/3V66).
It supports three-level mode selection (S1/S2), SMBus register access (slave address D2h), and dynamic output enable/disable per clock group. Spread spectrum is down-spread only, configurable via Control Register Bit 7, and VTTPWRGD# enables safe sampling of configuration inputs during power-up sequencing.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Max CPU Clock Frequency | 133 MHz - supports Pentium III/IV-class dual-processor motherboards with tight skew requirements (≤150 ps CPU-CPU skew) |
| Reference Input Frequency | 14.318 MHz ±200 ppm - matches standard PC crystal tolerance; enables stable PLL lock without external trimming |
| Spread Spectrum Range | Down-spread only, ±0.25% to ±0.5% - reduces peak EMI by spreading energy across 30–100 kHz bandwidth |
| CPU Output Skew | ≤150 ps - ensures matched timing across four differential CPU clock pairs for synchronous multi-core operation |
| PCI/3V66 Skew | ≤500 ps (PCI-PCI), ≤1.5 ns (3V66-PCI) - maintains setup/hold margins for 33-MHz PCI bus timing compliance |
| USB/DOT Jitter | ≤350 ps cycle-cycle - meets USB 1.1 full-speed (12 MHz) and audio codec timing stability requirements |
| Supply Voltage Range | 3.135 V to 3.465 V - compatible with standard 3.3V LVTTL logic rails; no power sequencing required |
| Power-Down Current | 25 mA (IREF = 2.32 mA) - enables low-power suspend states in ACPI S3/S4 modes without clock leakage |
Pinout & Package
The CY28329ZXC is housed in a 56-pin Thin Shrink Small Outline Package (TSSOP) with 0.5-mm pitch, JEDEC MO-153 compliant, and thermally enhanced for motherboard-level thermal dissipation.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| REF (Pin 56) | 14.318-MHz reference clock output | Provides buffered crystal reference for chipset PLLs or secondary clock synthesis stages |
| CPU0–CPU3 / CPU0#–CPU3# (Pins 44,45,48,49,51,52,53,54) | Differential CPU clock outputs | LVDS-compatible differential pairs driving CPU front-side bus; each pair supports 100/133 MHz with matched rise/fall times |
| PCI0–PCI6 (Pins 10,11,12,13,16,17,18) | Synchronous PCI clock outputs | 33-MHz CMOS clocks with ≤500 ps inter-output skew; individually controllable via SMBus or PCI_STOP# assertion |
| 3V66_0, 3V66_1/VCH (Pins 33,35) | 66-MHz/48-MHz selectable clocks | 3V66_0 fixed at 66 MHz; 3V66_1/VCH configurable via SMBus Bit 5 to serve as either 66-MHz or 48-MHz clock for VCH or graphics controller |
| USB, DOT (Pins 39,38) | Fixed 48-MHz clocks | Dedicated outputs for USB host controller and video dot clock; edge-rate programmable via SMBus Data Byte 5 |
| PD#, PCI_STOP# (Pins 25,34) | Active-low power-down and PCI stop controls | Hardware-driven signals enabling immediate clock gating without SMBus latency; PD# disables all outputs except REF |
| SCLK, SDATA (Pins 30,29) | SMBus interface | Two-wire serial interface (slave address D2h) for runtime reconfiguration of output enables, spread spectrum, and VCH mode |
| VDD_CORE, VDD_CPU, VDD_PCI, etc. (Pins 1,8,14,19,26,32,37,46,50) | Domain-specific power supplies | Eight independent 3.3V supply pins isolate noise between CPU, PCI, 3V66, and core PLL domains |
Key Features
| Feature | Design Value |
|---|---|
| Four differential CPU clock pairs | Enables simultaneous support for dual-socket Pentium III/IV platforms with <150 ps inter-pair skew and matched rise/fall characteristics |
| SMBus-configurable output enables | Per-clock-group control (CPU, PCI, 3V66, USB/DOT) allows dynamic power management and board-level test mode activation |
| Spread-spectrum EMI reduction | Down-spread modulation (±0.25–0.5%) lowers radiated emissions without requiring board-level filtering components |
| ACPI-compliant power-down | PD# and PCI_STOP# inputs provide hardware-triggered clock gating aligned with S3/S4 sleep states, reducing system standby current |
| Multi-domain power isolation | Separate VDD pins for CPU, PCI, 3V66, 48MHz, and core PLL minimize cross-domain noise coupling in high-density motherboard layouts |
| Configurable 48/66-MHz VCH clock | 3V66_1/VCH pin toggles between 48 MHz (USB/audio) and 66 MHz (AGP graphics) via SMBus Bit 5, eliminating need for external multiplexer |
Applications
| Desktop Motherboard Clocking | Workstation Multi-CPU Platform |
|---|---|
|
Use Scenario: ATX form-factor desktop motherboard with Intel Pentium 4 FSB 533/800 MHz and four PCI slots. IC Role / Device Role / Timing Role: Primary clock synthesizer generating CPU FSB clocks, PCI sync clocks, USB 48-MHz, and AGP 66-MHz clocks from single 14.318-MHz crystal. Use Value: Reduces BOM count by consolidating eight clock sources into one IC; spread spectrum cuts conducted EMI by >10 dBμV/m at 150 MHz. |
Use Scenario: Dual-socket Xeon-based workstation supporting AGP Pro graphics and multiple high-speed I/O cards. IC Role / Device Role / Timing Role: Central timing hub delivering matched 133-MHz differential CPU clocks, 66-MHz AGP clocks, and 33-MHz PCI clocks with <500 ps inter-bus skew. Use Value: Ensures deterministic timing across CPU, memory controller, and peripheral buses - critical for SMP cache coherency and real-time I/O latency. |
| Industrial Embedded Controller | Legacy ISA/PCI Hybrid System |
|
Use Scenario: Fanless industrial PC with extended temperature range (0°C to 70°C) and long-lifecycle component requirements. IC Role / Device Role / Timing Role: Single-chip clock source for CPU, PCI, USB, and ISA timing domains; SMBus enables firmware-controlled clock disable during idle states. Use Value: Eliminates discrete clock buffers and oscillators, improving MTBF and simplifying thermal design in sealed enclosures. |
Use Scenario: Medical imaging chassis integrating legacy ISA data acquisition cards alongside modern PCI-based image processing modules. IC Role / Device Role / Timing Role: Generates 33-MHz PCI clocks, 8-MHz ISA clocks (via 3V66 divider), 48-MHz USB, and 14.318-MHz reference for analog subsystems. Use Value: Maintains backward compatibility with ISA timing while enabling USB 1.1 connectivity - avoids dual-crystal solutions and layout complexity. |
Equivalent & Alternatives
Cypress CY28329ZXC has two verified drop-in alternatives with documented functional overlap and known trade-offs:
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| IDT 87301AGLFT | Single 133-MHz CPU output pair (vs. four); no SMBus interface; fixed 48-MHz USB clock only | Lacks multi-CPU support and runtime configurability; suitable for single-processor embedded designs | Select when cost sensitivity outweighs flexibility; requires external buffers for multi-CPU fanout |
| ICS 952005AF | Supports 166-MHz CPU clocks but lacks spread spectrum; uses 48-pin QFN instead of TSSOP | Better for high-FSB overclocking scenarios; unsuitable for EMI-constrained medical/automotive applications | Choose only if 133-MHz limit is insufficient and EMI certification is not required |
Compared with IDT 87301AGLFT and ICS 952005AF, the CY28329ZXC uniquely combines quad-CPU clock generation, SMBus configurability, spread-spectrum EMI suppression, and TSSOP packaging - making it the sole option for cost-sensitive, EMI-regulated, multi-socket x86 motherboard designs requiring field-upgradable timing behavior.
Availability
CY28329ZXC is available at Aetrix Electronics and suitable for desktop motherboard manufacturing, industrial embedded controller production, and legacy PCI/ISA hybrid system integration requiring stable component supply and long-term lifecycle support.
Supply support for CY28329ZXC includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Cypress Semiconductor (now part of Infineon Technologies) is a U.S.-based semiconductor company specializing in timing, memory, and programmable logic solutions for computing and industrial markets.
The CY28329 belongs to Cypress's high-integration clock synthesizer product line, designed specifically for x86 motherboard timing consolidation - reducing discrete clock components while maintaining strict jitter, skew, and EMI compliance for PC platform certification.
FAQ
What is the maximum allowable load capacitance on the USB and REF outputs?
The CY28329ZXC specifies a maximum capacitive load of 20–30 pF on USB and REF outputs. Exceeding 30 pF risks violating rise/fall time specs (0.5–2.0 ns) and increases cycle-cycle jitter beyond the guaranteed 350 ps limit. Layout best practices include minimizing trace length, avoiding stubs, and using series termination if driving >2 loads.
How does the VTTPWRGD# pin affect configuration sampling?
VTTPWRGD# is a level-sensitive strobe that tells the CY28329ZXC when S1, S2, and MULT0 inputs are valid for sampling during power-up. When VTTPWRGD# transitions LOW, the device latches those pin states and ignores subsequent changes. If VTTPWRGD# remains HIGH, configuration defaults apply - including 100-MHz CPU mode and spread spectrum disabled.
Can the 3V66_1/VCH pin be used simultaneously as both 48-MHz and 66-MHz outputs?
No. The 3V66_1/VCH pin is a single-terminal output that operates exclusively in one mode: either 48 MHz (when SMBus Control Register Bit 5 = 1) or 66 MHz (Bit 5 = 0). It cannot generate both frequencies concurrently. This pin replaces the need for an external mux but requires firmware coordination to avoid timing conflicts during mode switching.
What is the impact of disabling individual PCI outputs via SMBus versus asserting PCI_STOP#?
Asserting PCI_STOP# halts all PCI[0:6] outputs simultaneously and immediately, while SMBus disable (Data Byte 2/3 bits) provides selective, non-disruptive shutdown of individual PCI clocks. PCI_STOP# also affects PCI_F[0:2] free-running clocks only if their respective control bits (Data Byte 3 Bits 5–3) are set to 1 - offering layered control for ACPI power-state transitions and test-mode isolation.
CY28329ZXC Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Infineon Technologies
- Series:
- -
- Package/Case:
- 56-TFSOP (0.240", 6.10mm Width)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Type:
- Clock Driver, Clock/Frequency Synthesizer, Fanout Distribution, Spread Spectrum Clock Generator
- PLL:
- Yes
- Input:
- LVTTL, Crystal
- Output:
- Clock
- Number of Circuits:
- 1
- Ratio - Input:Output:
- 1:22
- Differential - Input:Output:
- No/Yes
- Frequency - Max:
- 133MHz
- Divider/Multiplier:
- Yes/No
- Voltage - Supply:
- 3.135V ~ 3.465V
- Operating Temperature:
- 0°C ~ 70°C
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 56-TSSOP II
CY28329ZXC FAQ
1.How can I place an order for CY28329ZXC through Aetrix?
Please submit a Request for Quotation (RFQ) for CY28329ZXC on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for CY28329ZXC reliable?
The price and inventory of CY28329ZXC are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for CY28329ZXC is usually 5 days.
3.What payment methods are accepted for CY28329ZXC?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for CY28329ZXC transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for CY28329ZXC?
CY28329ZXC orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your CY28329ZXC order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for CY28329ZXC?
For technical support, including CY28329ZXC datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your CY28329ZXC requirements.
6.How does Aetrix verify that CY28329ZXC is sourced from the original manufacturer or authorized distributors?
All CY28329ZXC products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that CY28329ZXC meets industry standards.
7.What is the process for return or replacement of CY28329ZXC?
All CY28329ZXC units undergo pre-shipment inspection (PSI). If there is an issue with CY28329ZXC, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The CY28329ZXC part is unused and in its original packaging.
Return procedure for CY28329ZXC:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
CY28329ZXC Tags
-
CD74HCT4046AM96
Texas Instruments
-
MC14046BDWR2G
onsemi
-
501MILFT
Renesas Electronics Corporation
-
CD74HC7046AM
Texas Instruments
-
CDCVF2505PWR
Texas Instruments
-
RC19004A100GNL#KB0
Renesas Electronics Corporation
-
SI5351A-B-GTR
Skyworks Solutions Inc.
-
CY2305SXI-1T
Infineon Technologies
-
570BILFT
Renesas Electronics Corporation
-
CDCE913PWR
Texas Instruments
-
CY2305SXI-1HT
Infineon Technologies
-
DS1086LU+T
Analog Devices Inc./Maxim Integrated
Tech Hub
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
LDO regulator guide covering low dropout voltage, power dissipation, thermal design, PSRR, output noise, capacitor stability, adjustable LDO circuits, LDO vs buck converter and datasheet selection chec…
Conditional Access Module guide covering CAM meaning, CI/CI+ interface, smart card authorization, DVB security workflow, TV and set-top box compatibility, internal electronics, ESD protection, connecto…
Guide to electronic component obsolescence covering EOL risk, PCN/PDN notices, last-time buy planning, replacement options, form-fit-function validation, counterfeit risk and BOM lifecycle management.
18650 battery guide covering lithium-ion cell basics, 3.6V/3.7V voltage, 4.2V charging, mAh and Wh capacity, protected cells, chargers, BMS, series-parallel packs, holders, welding and sourcing checks.…
Hall effect sensor guide covering working principle, linear and digital sensors, Arduino circuits, current sensing, speed detection, automotive applications, A3144 examples, signal filtering and datash…
Product Change Notification guide for electronic components, covering PCN meaning, PCN vs PDN/EOL, common change types, risk levels, form-fit-function review, engineering validation, BOM control, LTB/L…
A practical guide to blend door actuators, covering HVAC function, symptoms, location, AC and heater issues, reset and calibration, replacement cost, electrical diagnosis, compatibility checks, and rep…
