Infineon Technologies CY28339ZXC

Overview

CY28339ZXC from Cypress Semiconductor is a 48-pin TSSOP Intel CK408-compliant mobile clock synthesizer generating two differential CPU clocks (100/133 MHz), nine PCI clocks, five/six 3V66 outputs, dual 48 MHz USB/DOT clocks, one VCH clock, and a 14.318 MHz reference clock-all from a single 3.3V supply with SMBus programmability and spread-spectrum EMI reduction.

For engineers reviewing the CY28339ZXC datasheet, CY28339ZXC pinout, CY28339ZXC application, or CY28339ZXC equivalent, this device supports Intel mobile platform timing requirements including CPU clock switching, PCI bus synchronization, USB/DOT clock alignment, and dynamic spread-spectrum control via SMBus registers.

Technical Context

The CY28339ZXC integrates two independent PLLs: PLL1 generates CPU clocks and core synchronous outputs (3V66, PCI, PCIF), while PLL2 drives the 48 MHz USB/DOT/VCH domain with sub-nanosecond skew control. Both PLLs accept a 14.318 MHz crystal input (XIN/XOUT) and support hardware mode selection via S1/S2 pins.

SMBus interface (address D2/D3) enables real-time configuration of dial-a-frequency (N/R registers), dial-a-dB (spread-spectrum depth), output enables, and functional modes-including 3V66_1/VCH dual-mode selection (66 MHz SSCG vs. 48 MHz phase-aligned VCH) and PCI_STOP#/CPU_STOP# synchronized gating.

Key Specifications

Pinout & Package

48-pin TSSOP package (JEDEC MO-153AC), 0.5 mm pitch, body size 7.0 mm × 12.5 mm, exposed pad not electrically connected.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar mobile clock synthesizer applications.

Compared with ICS952006AGT and NB3N3020B, the CY28339ZXC uniquely delivers synchronized 48 MHz triple-output with sub-ns skew, full CK408 stop protocol support, and SMBus-accessible dial-a-frequency-making it irreplaceable for Intel mobile platforms requiring VCH alignment and dynamic EMI tuning.

Availability

CY28339ZXC is available at Aetrix Electronics and suitable for mobile notebook platforms, embedded industrial PCs, medical imaging controllers, and automotive infotainment head units requiring stable component supply and long-term lifecycle support.

Supply support for CY28339ZXC includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Cypress Semiconductor (now part of Infineon Technologies) is a U.S.-based semiconductor company specializing in high-performance timing, memory, and programmable logic solutions for computing and industrial markets.

The CY28339ZXC belongs to Cypress's CK408 Mobile Clock Synthesizer product line, designed specifically to meet Intel's mobile platform timing specifications-including CPU clock generation, PCI bus synchronization, USB/DOT clock alignment, and spread-spectrum EMI reduction.

FAQ

What is the function of the S2 pin, and how does its tri-level behavior affect operation?

The S2 pin is a 3.3V tri-level input (LOW < 0.8V, MID 1.0–1.8V, HIGH > 2.0V) that sets the base CPU clock ratio at power-up. When sampled at MID level during power-on, it latches a '0' into the internal state register-selecting the TCLK/2, TCLK/4, or TCLK/8 mode depending on S1. This hardware mode determines the P-value used by the PLL for frequency synthesis and cannot be overridden by SMBus writes after power-up.

How does the 3V66_1/VCH pin switch between 66 MHz and 48 MHz modes, and what is the impact on timing?

The 3V66_1/VCH pin switches between 66 MHz (default, SSCG-capable) and 48 MHz (VCH mode) via SMBus Byte0 Bit5. When configured as VCH, it achieves <1 ns pin-to-pin skew with USB_48MHz and DOT_48MHz-enabling precise video/audio synchronization. Switching from 66 MHz to 48 MHz may cause a transient glitch, so it must occur at system power-on before clocks are enabled.

Can the CY28339ZXC generate non-integer CPU clock ratios, and how is this achieved?

Yes-the CY28339ZXC supports non-integer CPU clock ratios via SMBus-accessible Dial-a-Frequency registers (Byte8/N and Byte9/R). Writing custom N/R values modifies the PLL feedback divider without altering S1/S2 hardware settings, allowing fine-resolution CPU frequency tuning (e.g., 124.5 MHz) while preserving fixed ratios for PCI, USB, and other derived clocks.

What is the timing relationship between PD# assertion and clock shutdown?

Upon PD# assertion (LOW), the device synchronizes to CPUC clock edges: after two consecutive rising edges, PCIF stops on its next HIGH-to-LOW transition, then 66BUFF stops similarly, followed by all remaining clocks-including CPUT driven HIGH at 2×IREF and CPUC undriven. Total shutdown completes within one 66 MHz cycle, ensuring glitch-free, synchronous power-down without metastability.